----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 25.10.2023 14:17:15
-- Design Name: 
-- Module Name: ADC_Interface - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADC_Interface is port
    (
    CLK              : in std_logic;
    -- reset            : in std_logic;
    --enable_in        : in std_logic;
    Real_in_from_ADC : in std_logic_vector(9 downto 0);--receiver side i/p
    -- imag_in_from_ADC : in std_logic_vector(9 downto 0); --receiver side i/p

    Dout            : out std_logic_vector(9 downto 0);--receiver side 0/p
    -- Dout2            : out std_logic_vector(9 downto 0);--receiver side o/p

    CLK_out          : out std_logic 
-- ADC_CLK2 : out std_logic;
   --  enable_out       : out std_logic
    );
end ADC_Interface;

architecture Behavioral of ADC_Interface is

begin


process(CLK)
    begin
        -- if  reset = '1' then
           -- enable_out  <= '0';
            -- Dout1       <= (others=>'0');
            -- Dout2       <=  (others=>'0');

        if rising_edge (CLK) then

            Dout       <= Real_in_from_ADC ;
            -- Dout2       <= imag_in_from_ADC;
           -- enable_out  <= enable_in;

        end if;

end process;

CLK_out <= CLK ;
-- ADC_CLK2<=CLK_SAMP;

end Behavioral;