Hi, I am requesting some help because I am completly stuck in my VHDL
project. All of my VHD files do compile without any errors, but when I
want to simulate the whole block on Modelsim, here is what I get:
```
# ** Fatal: (vsim-3807) Types do not match between component and entity
for port "nibble1".
# Time: 0 ps Iteration: 0 Instance: /myadder_vhd_vec_tst/i1 File:
Adder.vho Line: 37
# FATAL ERROR while loading design
# Error loading design
Error loading design
# End time: 09:47:42 on May 31,2021, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0
Error.
```
This should be an easy error to spot, but I've checked my types a
thousand times, they all seem to match. Here's my code. Once again they
all compile, but I get these errors only at simulation on Modelsim.
1 | library IEEE;
|
2 | USE IEEE.STD_LOGIC_1164.all;
|
3 | USE IEEE.NUMERIC_STD.all;
|
4 |
|
5 | ENTITY myAdder IS
|
6 |
|
7 | PORT
|
8 | (
|
9 | nibble1, nibble2 : IN unsigned(3 downto 0);
|
10 |
|
11 | sum : OUT unsigned(3 downto 0);
|
12 | carry_out : OUT STD_LOGIC
|
13 | );
|
14 |
|
15 | END myAdder;
|
16 |
|
17 | ARCHITECTURE myArch OF myAdder IS
|
18 | signal temp : unsigned(4 downto 0);
|
19 | BEGIN
|
20 |
|
21 | temp <= ("0" & nibble1) + nibble2;
|
22 |
|
23 | sum <= temp(3 downto 0);
|
24 | carry_out <= temp(4);
|
25 |
|
26 | END myArch;
|
The error specifically mentions the port "nibble1" which is strange.
Thanks.
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