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Forum: FPGA, VHDL & Verilog Types do not match between component and entity at Simulation on Modelsim


von Nima (Guest)


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Hi, I am requesting some help because I am completly stuck in my VHDL 
project. All of my VHD files do compile without any errors, but when I 
want to simulate the whole block on Modelsim, here is what I get:
```
# ** Fatal: (vsim-3807) Types do not match between component and entity 
for port "nibble1".
#    Time: 0 ps  Iteration: 0  Instance: /myadder_vhd_vec_tst/i1 File: 
Adder.vho Line: 37
# FATAL ERROR while loading design
# Error loading design
Error loading design

# End time: 09:47:42 on May 31,2021, Elapsed time: 0:00:01
# Errors: 1, Warnings: 0

Error.
```
This should be an easy error to spot, but I've checked my types a 
thousand times, they all seem to match. Here's my code. Once again they 
all compile, but I get these errors only at simulation on Modelsim.
1
library IEEE;
2
USE IEEE.STD_LOGIC_1164.all;
3
USE IEEE.NUMERIC_STD.all;
4
5
ENTITY myAdder IS
6
7
  PORT
8
  (
9
    nibble1, nibble2 : IN unsigned(3 downto 0);
10
    
11
    sum              : OUT unsigned(3 downto 0);    
12
    carry_out        : OUT STD_LOGIC
13
  );
14
  
15
END myAdder;
16
17
ARCHITECTURE myArch OF myAdder IS
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  signal temp : unsigned(4 downto 0);
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BEGIN
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  temp <= ("0" & nibble1) + nibble2;
22
  
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  sum <= temp(3 downto 0);
24
  carry_out <= temp(4);
25
  
26
END myArch;
The error specifically mentions the port "nibble1" which is strange.
Thanks.

von Dussel (Guest)


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And where is myAdder used? I suspect the error to be in the component 
instantiation.
In the top level file you probably have something like
1
component myAdder IS
2
  PORT
3
  (
4
5
    nibble1, nibble2 : IN unsigned(3 downto 0);
6
    sum              : OUT unsigned(3 downto 0);    
7
    carry_out        : OUT STD_LOGIC
8
  );
9
end component;
1
adder : myAdder
2
port map(
3
  nibble1 => ...,
4
  nibble2 => ...,
5
  ...)
Check if everything is correct there.

PS: For me the text indentation in the code view is very high. Is that 
the same for everyone?

von Lerninstructor (Guest)


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This is also wrong:
<code>
temp <= ("0" & nibble1) + nibble2;
</code>


Please, resume the lesson reagarding the difference between '0' and "0". 
Also, re-read the specification regarding array-types and the relation 
to range - definition.

> but I've checked my types a
> thousand times, they all seem to match.

You're lying. Hint: there can be more than just a single type definition 
for 'unsigned' in a code, this depends on the different libraries 
(ieee.numeric_standard",ieee.numeric_bit ) included.


--
Dussel wrote:
> Check if everything is correct there.
>
> PS: For me the text indentation in the code view is very high. Is that
> the same for everyone?

Yes, the vhdl syntax highlight ist quit broken here.

von Lothar M. (lkmiller) (Moderator)


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Dussel wrote:
> PS: For me the text indentation in the code view is very high. Is that
> the same for everyone?
Yes, its a problem within the English forum. I reported it to Andreas, 
but he seems busy.

The other tags [pre], [c], [code] don't work much better...

von Lerninstructor (Guest)


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Lothar M. wrote:
> Dussel wrote:
>> PS: For me the text indentation in the code view is very high. Is that
>> the same for everyone?
> Yes, its a problem within the English forum.

Not in general, this thread in the 'English forum' looks pretty:
https://embdev.net/topic/518643#new

von Lerninstructor (Guest)


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I swithed off "sanfter Bildlauf" and "Automatischen Bildlauf aktivieren" 
in the browser settings and it looks much better:

von Dussel (Guest)


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I opened a thread on the german site. We don't have to discuss this 
problem here.

von Lerninstructor (Guest)


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Dussel wrote:
> I opened a thread on the german site. We don't have to discuss this
> problem here.

Link, please ;-)

von Dussel (Guest)


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Beitrag "VHDL-Code: Einrückung zu groß"
I wrote it can be closed, but if there are new informations, it might 
stay open.

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