Hello everyone I have a task that says : i will need to put 8 unsigned inputs(8 numbers, 8 bit per input) and i have to find the biggest number and then export it to the output. Can someone help me with the code?

Take a look at Fig 11 on Page 10: http://dbis.cs.tu-dortmund.de/cms/de/publications/2012/sorting-networks/sorting-networks.pdf

MariosBon wrote: > *HELP VHDL CODE * I can't see no VHDL to help. > Can someone help me with the code? Let's try to do it this way: you show some code and ask a particular question about a specific problem. Just to say: "do my homework pls" isn't enough.

:
Edited by Moderator

Just for a start, here a simple subcomponent:

1 | library ieee; |

2 | use ieee.std_logic_1164.all; |

3 | use ieee.std_logic_signed.all; |

4 | use ieee.std_logic_arith.all; |

5 | |

6 | |

7 | entity cmpx is |

8 | port( |

9 | data_a_i : in std_logic_vector(7 downto 0); |

10 | data_b_i : in std_logic_vector(7 downto 0); |

11 | greates_o : out std_logic_vector(7 downto 0)); |

12 | end port; |

13 | |

14 | architecture behave of cmpx is |

15 | |

16 | ```
begin
``` |

17 | greatest_o <= data_a_i when data_a_i > data_b_i else |

18 | data_b_i; |

19 | end architecture behave; |

ty for the reply,,, for 2 numbers its easy but what about 8? i thought that i can put the first number to a "max" variable and the compare that variable to the numbers but i am not sure how i can write these thoughts on vhdl code.

1 | library ieee; |

2 | USE ieee.std_logic_1164.all; |

3 | Use ieee.numeric_std.all; |

4 | USE ieee.std_logic_unsigned.all; |

5 | |

6 | |

7 | ENTITY compare8 IS |

8 | port(a,b,c,d,e,f,g,h : in std_logic_vector ( 7 downto 0); |

9 | ( exod:out std_logic_vector (7 downto 0)); |

10 | end compare8 |

11 | |

12 | |

13 | ARCHITECTURE behaviour OF compare8 IS |

14 | m : std_logic_vector(7 downto 0); |

15 | ```
BEGIN
``` |

16 | m<=a; |

( and here is where my brain freeze and i cant continue the programm..i try to use the comand IF but i stuck after the first comparison)

:
Edited by Moderator

The problem is not VHDL. The problem is that you have no clue how to find the largest of 8 numbers. So ... just describe in natural language, here, how to get the largest of 8 numbers. This is step 1. When you know how to find the largest number, then we can think of how to do this in vhdl.

FPGA NOTFALLSEELSORGE wrote: > then we can think of how to do this in vhdl. And then pls wrap your VHDL code into the VHDL tags as described here above each edit box in "Formatting options".

1 | |

2 | Use ieee.numeric_std.all; |

3 | USE ieee.std_logic_unsigned.all; |

Never ever both together! In real life these two lines beneath each other are a reasonable reason to get fired.

:
Edited by Moderator

MariosBon wrote: > ty for the reply,,, for 2 numbers its easy but what about 8? Just use the 2-> 1 subcomponents and GENERATE directive to construct -first layer: with 4 subcomponents to get 4 results of 8 inputs top-level -second layer: with 2 subcomponents to get 2 results of 4 inputs (all 4 outputs of 1-layer) -third layer: with ... ( this shall be easy to guess) https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.55.6397&rep=rep1&type=pdf

Gehilfe des Stellvertreters z. bes. Verwendung wrote: > Just use the 2-> 1 subcomponents and GENERATE directive to construct Or do a simple loop with a compare and an assignment to a variable. But I think, FPGA NOTFALLSEELSORGE is correct: first there must be a solution on a sheet of paper. In the best case as a schematic. Then its fairly easy todescribethis schematic with the hardwaredescriptionlanguage VHDL.

Lothar M. wrote: > But I think, FPGA NOTFALLSEELSORGE is correct: first there must be a > solution on a sheet of paper. In the best case as a schematic. And the concept used here is called a (binary) tree - structure , or in German Language 'Baumstruktur' ... In this particular case see "comparing tree" https://www.pickeringtest.com/de-de/kb/hardware-topics/switching-architectures/comparing-tree-and-conventional-mux-architectures

in natural language : lets say that we have 8 numbers .. lets put the first number in a viarable ( max ) and then we compare the max first with b , if the number b > max then the max will take be the number b else the max variable will remain the same , and then we must compare the max viarable to the other numbers , at the end we have to assign the max value to the output...... thats how i think it will work.

or i can compare it in multiple (if) comands but i dont know if it is syntictically correct like :

1 | IF ( A < B) THEN |

2 | O1<= B; ELSE |

3 | O1<=A; |

4 | IF ( C < D ) THEN |

5 | O2<=D; ELSE |

6 | O2<=C; |

7 | IF ( E < F ) THEN |

8 | O3<=F; ELSE |

9 | O3<=E; |

10 | IF ( G < H ) THEN |

11 | O4<= H ; ELSE |

12 | 04<= G ; |

13 | IF (01 < 02 ) THEN |

14 | S<= 02 ; ELSE |

15 | S<= 01; |

16 | IF (O3 < O4) THEN |

17 | Y<= 04; ELSE |

18 | Y<=03; |

19 | IF (S < Y ) THEN |

20 | M<=Y; ELSE |

21 | M<=S; |

( This is my second thought but i think is really wrong)

:
Edited by Moderator

Well you described one method in natural language and in "code" you wrote an different method. But yes, both will work. But don't use signals names 04 or so, tzhey have to start with a letter. Now it is time to write correct vhdl. You may choose between a clocked pipeline or a combinatorical solution.

FPGA NOTFALLSEELSORGE wrote: > But don't use signals names 04 or so, tzhey have to start with a letter. And they may be mixed up with o4 or so... MariosBon wrote: > ( This is my second thought but i think is really wrong) The thought is ok, but you will encounter some weird results in simulation due to how signals behave. I would try it simply without any process. Somehow like that:

1 | ```
:
``` |

2 | signal ab, cd, ef, gh, abcd, efgh : std_logic_vector( 7 downto 0); |

3 | ```
:
``` |

4 | ```
:
``` |

5 | ab <= a when a>b else b; |

6 | cd <= c when c>d else d; |

7 | ef <= e when e>f else f; |

8 | gh <= g when g>h else h; |

9 | abcd <= ab when ab>cd else cd; |

10 | efgh <= ef when ef>gh else gh; |

11 | max <= abcd when abcd>efgh else efgh; |

12 | ```
:
``` |

Hello guys, after some reading and help from you i wrote the programm just like that , any correction accepted. ( This is my first program in vhdl )

1 | LIBRARY ieee; |

2 | USE ieee.std_logic_1164.all; |

3 | USE ieee.numeric_std.all; |

4 | ```
------------------------------
``` |

5 | |

6 | ENTITY compare8 IS |

7 | PORT ( a,b,c,d,e,f,g,h : IN std_logic_vector (7 downto 0); |

8 | max : OUT std_logic_vector (7 downto 0); |

9 | END compare8; |

10 | ```
-----------------------------
``` |

11 | ARCHITECTURE behaviour OF compare8 IS |

12 | SIGNAL (a_uns,b_uns,c_uns,d_uns,e_uns,f_uns,g_uns,h_uns,ab_uns,cd_uns,ef_uns,gh_uns,abcd_uns,efgh_uns,high_uns : UNSIGNED(7 downto 0); |

13 | |

14 | ```
BEGIN
``` |

15 | a_uns<=UNSIGNED(a); |

16 | b_uns<=UNSIGNED(b); |

17 | c_uns<=UNSIGNED(c); |

18 | d_uns<=UNSIGNED(d); |

19 | e_uns<=UNSIGNED(e); |

20 | f_uns<=UNSIGNED(f); |

21 | g_uns<=UNSIGNED(g); |

22 | h_uns<=UNSIGNED(h); |

23 | |

24 | |

25 | ab_uns<= a_uns WHEN a_uns>b_uns ELSE b_uns; |

26 | |

27 | cd_uns<= c_uns WHEN c_uns>d_uns ELSE d_uns; |

28 | |

29 | ef_uns<= e_uns WHEN e_uns>f_uns ELSE f_uns; |

30 | |

31 | hg_uns<= h_uns WHEN h_uns>g_uns ELSE g_uns; |

32 | |

33 | abcd_uns<= ab_uns WHEN ab_uns>cd_uns ELSE cd_uns; |

34 | |

35 | efgh_uns<= ef_uns WHEN ef_uns>gh_uns ELSE gh_uns; |

36 | |

37 | high_uns<= abcd_uns WHEN abcd_uns>efgh_uns ELSE efgh_uns; |

38 | |

39 | max<=high_uns; |

40 | |

41 | END behaviour; |

MariosBon wrote: > any correction accepted Run a simulation and check out, what the simulator says to the code.