I have a task that says : i will need to put 8 unsigned inputs(8
numbers, 8 bit per input) and i have to find the biggest number and then
export it to the output.
Can someone help me with the code?
MariosBon wrote:> *HELP VHDL CODE *
I can't see no VHDL to help.
> Can someone help me with the code?
Let's try to do it this way: you show some code and ask a particular
question about a specific problem. Just to say: "do my homework pls"
ty for the reply,,, for 2 numbers its easy but what about 8? i thought
that i can put the first number to a "max" variable and the compare that
variable to the numbers but i am not sure how i can write these thoughts
on vhdl code.
The problem is not VHDL. The problem is that you have no clue how to
find the largest of 8 numbers.
So ... just describe in natural language, here, how to get the largest
of 8 numbers. This is step 1. When you know how to find the largest
number, then we can think of how to do this in vhdl.
Gehilfe des Stellvertreters z. bes. Verwendung wrote:> Just use the 2-> 1 subcomponents and GENERATE directive to construct
Or do a simple loop with a compare and an assignment to a variable.
But I think, FPGA NOTFALLSEELSORGE is correct: first there must be a
solution on a sheet of paper. In the best case as a schematic. Then its
fairly easy to describe this schematic with the hardware description
in natural language : lets say that we have 8 numbers .. lets put the
first number in a viarable ( max ) and then we compare the max first
with b , if the number b > max then the max will take be the number b
else the max variable will remain the same , and then we must compare
the max viarable to the other numbers , at the end we have to assign the
max value to the output...... thats how i think it will work.
Well you described one method in natural language and in "code" you
wrote an different method. But yes, both will work.
But don't use signals names 04 or so, tzhey have to start with a letter.
Now it is time to write correct vhdl. You may choose between a clocked
pipeline or a combinatorical solution.
FPGA NOTFALLSEELSORGE wrote:> But don't use signals names 04 or so, tzhey have to start with a letter.
And they may be mixed up with o4 or so...
MariosBon wrote:> ( This is my second thought but i think is really wrong)
The thought is ok, but you will encounter some weird results in
simulation due to how signals behave.
I would try it simply without any process. Somehow like that: