Forum: FPGA, VHDL & Verilog *HELP VHDL CODE *

Hello everyone
 I have  a task that says  : i will need to put 8 unsigned  inputs(8 
numbers, 8 bit per input) and i have to find the biggest number and then 
export it to the output.
Can someone help me with the code?

Take a look at Fig 11 on Page 10:
http://dbis.cs.tu-dortmund.de/cms/de/publications/2012/sorting-networks/sorting-networks.pdf

Just finding the largest number is of course not that complex.

Just for a start, here a simple subcomponent:

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library ieee;

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use ieee.std_logic_1164.all;

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use ieee.std_logic_signed.all;

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use ieee.std_logic_arith.all;

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entity cmpx is

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  port(

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    data_a_i  : in  std_logic_vector(7 downto 0);

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    data_b_i  : in  std_logic_vector(7 downto 0);

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    greates_o : out std_logic_vector(7 downto 0));

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end port;

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architecture behave of cmpx is

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begin

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  greatest_o <= data_a_i when data_a_i > data_b_i else

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                data_b_i;

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end architecture behave;

ty for the reply,,, for 2 numbers its easy but what about 8? i thought 
that i can put the first number to a "max" variable and the compare that 
variable to the numbers but i am not sure how i can write these thoughts 
on vhdl code.

sorry for the confusion

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library ieee;

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USE ieee.std_logic_1164.all;

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Use ieee.numeric_std.all;

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USE ieee.std_logic_unsigned.all;

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ENTITY compare8 IS

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       port(a,b,c,d,e,f,g,h : in std_logic_vector ( 7 downto 0);

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           ( exod:out std_logic_vector (7 downto 0));

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end compare8

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ARCHITECTURE  behaviour OF compare8 IS

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        m : std_logic_vector(7 downto 0);

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BEGIN 

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     m<=a;

( and here is where my brain freeze and i cant continue the programm..i 
try to use the comand IF but i stuck after the first comparison)

The problem is not VHDL. The problem is that you have no clue how to 
find the largest of 8 numbers.

So ... just describe in natural language, here, how to get the largest 
of 8 numbers. This is step 1. When you know how to find the largest 
number, then we can think of how to do this in vhdl.

MariosBon wrote:
> ty for the reply,,, for 2 numbers its easy but what about 8?

Just use the 2-> 1 subcomponents and  GENERATE directive to construct

-first  layer: with  4 subcomponents to get 4 results of 8 inputs 
top-level
-second layer: with  2 subcomponents to get 2 results of 4 inputs (all 4 
outputs of 1-layer)
-third  layer: with ... ( this shall be easy to guess)

https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.55.6397&rep=rep1&type=pdf

Lothar M. wrote:
> But I think, FPGA NOTFALLSEELSORGE is correct: first there must be a
> solution on a sheet of paper. In the best case as a schematic.

And the concept used here is called a (binary) tree - structure , or in 
German Language 'Baumstruktur' ...

In this particular case see "comparing tree"
https://www.pickeringtest.com/de-de/kb/hardware-topics/switching-architectures/comparing-tree-and-conventional-mux-architectures

ok guys thanks for the advice i will try my best!

in natural language : lets say that we have 8 numbers .. lets put the 
first number in a viarable ( max ) and then we compare the max first 
with b , if the number b > max then the max will take be the number b 
else the max variable will remain the same , and then we must compare 
the max viarable to the other numbers , at the end we have to assign the 
max value to the output...... thats how i think it will work.

or i can compare it in multiple (if) comands but i dont know if it is 
syntictically correct like :

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IF ( A < B) THEN

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     O1<= B; ELSE

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     O1<=A;

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IF ( C < D ) THEN

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     O2<=D; ELSE

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     O2<=C;

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IF ( E < F ) THEN

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    O3<=F; ELSE

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    O3<=E;

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IF ( G < H ) THEN

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    O4<= H ; ELSE

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    04<= G ;

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IF (01 < 02 ) THEN

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    S<= 02 ; ELSE

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    S<= 01;

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IF (O3 < O4) THEN

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   Y<= 04;   ELSE

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   Y<=03;

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IF (S < Y ) THEN

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    M<=Y;   ELSE

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    M<=S;

( This is my second thought but i think is really wrong)

Well you described one method in natural language and in "code" you 
wrote an different method. But yes, both will work.

But don't use signals names 04 or so, tzhey have to start with a letter.

Now it is time to write correct vhdl. You may choose between a clocked 
pipeline or a combinatorical solution.

Hello guys, after some reading and help from you i wrote the programm 
just like that , any correction accepted. ( This is my first program in 
vhdl )

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 LIBRARY ieee;

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 USE ieee.std_logic_1164.all;

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 USE ieee.numeric_std.all;

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------------------------------

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ENTITY compare8 IS

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      PORT ( a,b,c,d,e,f,g,h : IN std_logic_vector (7 downto 0);

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             max : OUT std_logic_vector (7 downto 0);

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END compare8;

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-----------------------------

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ARCHITECTURE behaviour OF compare8 IS

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     SIGNAL (a_uns,b_uns,c_uns,d_uns,e_uns,f_uns,g_uns,h_uns,ab_uns,cd_uns,ef_uns,gh_uns,abcd_uns,efgh_uns,high_uns : UNSIGNED(7 downto 0);

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     BEGIN 

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   a_uns<=UNSIGNED(a);

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   b_uns<=UNSIGNED(b);

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   c_uns<=UNSIGNED(c);

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   d_uns<=UNSIGNED(d);

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   e_uns<=UNSIGNED(e);

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   f_uns<=UNSIGNED(f);

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   g_uns<=UNSIGNED(g);

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   h_uns<=UNSIGNED(h);

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 ab_uns<= a_uns WHEN a_uns>b_uns ELSE b_uns;

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 cd_uns<= c_uns WHEN c_uns>d_uns ELSE d_uns;

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 ef_uns<= e_uns WHEN e_uns>f_uns ELSE f_uns;

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 hg_uns<= h_uns WHEN h_uns>g_uns ELSE g_uns;

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 abcd_uns<= ab_uns WHEN ab_uns>cd_uns ELSE cd_uns;

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 efgh_uns<= ef_uns WHEN ef_uns>gh_uns ELSE gh_uns;

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 high_uns<= abcd_uns WHEN abcd_uns>efgh_uns ELSE efgh_uns;

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 max<=high_uns;

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END behaviour;