vcom-1576 error with expecting BEGIN

SilentRoar Guest 2021-05-29 00:56 #6708321

Rate this post

•	▲ useful ▼ not useful

Hello!

I'm newbie in this topic, so sorry if I say something dumb. I have the 
following code, which always comeback with a 'vcom-1576 error expecting 
BEGIN at line 12 in ModelSim. What I'm missing from the code?

Thanks for the help in advance!

library IEEE;
use IEEE.std_logic_1164.all;
entity MODULE is
port ( X,Y,BIN : in std_logic_vector(3 downto 0);
  D  : out std_logic_vector(3 downto 0);
  BOUT : out std_logic_vector
end MODULE;
architecture behavioral of MODULE is
p1: process(X, Y,BIN);
variable var_D, var_BIN : std_logic_vector(3 downto 0);
var_BIN := BIN;
for j in 0 to 3 loop
var_D(j) := X(j) xor Y(j) xor var_BIN;
var_BOUT(j) := (not X(j) and Y(j)) or (not X(j) and var_BIN(j)) or (Y(j) and var_BIN(j));
end loop;
D<=var_D;
BOUT<=var_BOUT;
end process p1;
end behavioral;

Attached files:

co.vhd (573 Bytes) | highlighted code

Reply Quote Edit Move Thread sperren Anmeldepflicht aktivieren Anpinnen Delete topic Thread mit anderem zusammenführen Report post

-gb- Guest 2021-05-29 10:42 #6708538

Rate this post

•	▲ useful ▼ not useful

The word "begin" is missing. This is exactly what the error message 
says.

Reply Quote Edit Delete Report post

SilentRoar Guest 2021-05-29 12:18 #6708653

Rate this post

•	▲ useful ▼ not useful

von -gb-, thank you for understanding the error message, but my problem 
is, where is the begin missing? Because in my code there is the begin at 
line 14, and I don't understand why the program says it's missing...

Reply Quote Edit Delete Report post

FPGA NOTFALLSEELSORGE Guest 2021-05-29 12:22 #6708655

Rate this post

•	▲ useful ▼ not useful

At line 12.

-gb- wrote:
> This is exactly what the error message says.

Reply Quote Edit Delete Report post

FPGA NOTFALLSEELSORGE Guest 2021-05-29 12:24 #6708658

Rate this post

•	▲ useful ▼ not useful

Take a look also at 
https://www.ics.uci.edu/~jmoorkan/vhdlref/architec.html

Reply Quote Edit Delete Report post

Gustl B. (-gb-) 2021-05-29 12:32 #6708673

Rate this post

•	▲ useful ▼ not useful

Formatting helps to finde errors. I attatched a formatted version. The 
";" in
p1: process(X, Y,BIN);
is a bug.

There is also no need for variables. So you process boils down to

process (X, Y,BIN) begin
  for j in 0 to 3 loop
    D(j)    := X(j) xor Y(j) xor BIN;
    BOUT(j) := (not X(j) and Y(j)) or (not X(j) and BIN(j)) or (Y(j) and 
BIN(j));
  end loop;
end process;

EDIT: REMOVED VHDL TAGS BECAUSE THEY BREAK FORMATTING !!!!!!1111elf!

Attached files:

co.vhd (687 Bytes) | highlighted code

Reply Quote Edit Delete Report post