vcom-1576 error with expecting BEGIN

SilentRoar Guest #6708321
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Hello!

I'm newbie in this topic, so sorry if I say something dumb. I have the 
following code, which always comeback with a 'vcom-1576 error expecting 
BEGIN at line 12 in ModelSim. What I'm missing from the code?

Thanks for the help in advance!

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library IEEE;

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use IEEE.std_logic_1164.all;

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entity MODULE is

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port ( X,Y,BIN : in std_logic_vector(3 downto 0);

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  D  : out std_logic_vector(3 downto 0);

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  BOUT : out std_logic_vector

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  );

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end MODULE;

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architecture behavioral of MODULE is

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p1: process(X, Y,BIN);

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variable var_D, var_BIN : std_logic_vector(3 downto 0);

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begin

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var_BIN := BIN;

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for j in 0 to 3 loop

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var_D(j) := X(j) xor Y(j) xor var_BIN;

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var_BOUT(j) := (not X(j) and Y(j)) or (not X(j) and var_BIN(j)) or (Y(j) and var_BIN(j));

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end loop;

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D<=var_D;

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BOUT<=var_BOUT;

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end process p1;

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end behavioral;
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SilentRoar Guest #6708653
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von -gb-, thank you for understanding the error message, but my problem 
is, where is the begin missing? Because in my code there is the begin at 
line 14, and I don't understand why the program says it's missing...
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Gustl B. #6708673
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Formatting helps to finde errors. I attatched a formatted version. The 
";" in
p1: process(X, Y,BIN);
is a bug.

There is also no need for variables. So you process boils down to

process (X, Y,BIN) begin
  for j in 0 to 3 loop
    D(j)    := X(j) xor Y(j) xor BIN;
    BOUT(j) := (not X(j) and Y(j)) or (not X(j) and BIN(j)) or (Y(j) and 
BIN(j));
  end loop;
end process;

EDIT: REMOVED VHDL TAGS BECAUSE THEY BREAK FORMATTING !!!!!!1111elf!
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