library IEEE;
use IEEE.std_logic_1164.all;

entity MODULE is port(
	X    : in std_logic_vector(3 downto 0);
	Y    : in std_logic_vector(3 downto 0);
	BIN  : in std_logic_vector(3 downto 0);
	D    : out std_logic_vector(3 downto 0);
	BOUT : out std_logic_vector);
end MODULE;

architecture behavioral of MODULE is

begin

p1: process (X, Y,BIN)
	variable var_D, var_BIN : std_logic_vector(3 downto 0);
begin
	var_BIN := BIN;
	for j in 0 to 3 loop
		var_D(j)    := X(j) xor Y(j) xor var_BIN;
		var_BOUT(j) := (not X(j) and Y(j)) or (not X(j) and var_BIN(j)) or (Y(j) and var_BIN(j));
	end loop;
	D    <= var_D;
	BOUT <= var_BOUT;
end process p1;

end behavioral;