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Forum: FPGA, VHDL & Verilog HELP-VHDL-CODE


von Merima D. (Company: student) (merimado)


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Hello everyone! I need help for this task, so if anyone can help me, I 
will be grateful 🙏

The digital system has 6 inputs (in0, in1, in2, in3, in4, in5) and two 
outputs (out0, out1).
Out0 will be in state "1" if an odd number "1" is detected at the 
inputs, while output out1 will be in "1" if at least three bits are in 
the state "1".
Develop a VHDL model of a given digital system and write a testbench 
probram that will determine the output of system for all possible input 
bit combinations.

von Dussel (Guest)


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You did not ask any specific question.
A general answer to your 'question' would be: You need to write code 
that sets Out0 high, if there is an odd number of ones on the input and 
set Out1 high, if at least three of the inputs are high.

If you have more specific questions, you can ask, of course.

von Gustl B. (-gb-)


Attached files:

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And ... here is a low-tech solution. Your teacher will not accept this! 
Use the testbench and write a better solution, count the bits, you may 
use variables.

von Lothar M. (lkmiller) (Moderator)


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: Edited by Moderator
von Gustl B. (-gb-)


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Bits zählen geht auch so:

counter <= ("00" & in5) + ("" & in4) + ("" & in3) + ("" & in2) + ("" & 
in1) + ("" & in0);

von Mampf (Guest)


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There is something (trivially) more clever for out0:
1
out0 <= in0 xor in1 xor in2 xor in3 xor in4 xor in5

von Mampf (Guest)


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Hmm ... what happend to the formatting ...

strange ... again:
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out0 <= in0 xor in1 xor in2 xor in3 xor in4 xor in5

von Mampf (Guest)


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out0 <= in0 xor in1 xor in2 xor in3 xor in4 xor in5

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