library ieee; use ieee.std_logic_1164.all; use IEEE.NUMERIC_STD.ALL; entity tb_ones is end tb_ones; architecture tb of tb_ones is component ones is port( in5 : in std_logic; in4 : in std_logic; in3 : in std_logic; in2 : in std_logic; in1 : in std_logic; in0 : in std_logic; out1 : out std_logic; out0 : out std_logic); end component; signal in_vector: std_logic_vector(5 downto 0):=(others => '0'); signal out1 : std_logic:='0'; signal out0 : std_logic:='0'; begin process begin wait for 10 ns; in_vector <= std_logic_vector(unsigned(in_vector) +1); end process; UUT: ones port map( in5 => in_vector(5), in4 => in_vector(4), in3 => in_vector(3), in2 => in_vector(2), in1 => in_vector(1), in0 => in_vector(0), out1 => out1, out0 => out0); end;