unexpected behavior of non-blocking assignment in an priority arbiter

Jimmy Z. OP #6655799
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I am a hdl noob currently experimenting with various styles of fsm.
My module is a simple priority arbiter. The non-blocking assignment 
statement is not behaving  the way I expected. On line 17 and 18 there 
are two non-blocking assignments, but they don't occur on the same 
cycle... the first one (gnt0 <= #1 0) occurs on cycles later then the 
ensuing assign(state <= next_state)... can someone explain to me why I 
attached the simulation result and complete source code for your 
reference.

1
always @(posedge clk) 

2
 begin : OUTPUT_LOGIC

3
   if (reset) begin

4
     gnt0 <= #1 0;

5
     gnt1 <= #1 0;

6
     state <= #1 IDLE;

7
   end else begin

8
     $monitor(" time for state assignment %d is %d \n",state, $time);

9
     case (state)

10
       IDLE: begin

11
         $display("set both gnt0 and gnt1 0");

12
          state <= #1 next_state;

13
         gnt0<=  #1 0;

14
                gnt1<=  #1 0;

15
       end

16
       GNT0: begin

17
         gnt0 <= #1 1;

18
          state <= #1 next_state;

19
       end

20
       GNT1: begin

21
        $display(" time for gnt1 assertion is %d ", $time); 

22
         gnt1 <= #1 1;

23
         state <= #1 next_state;

24
        $display(" gnt1 is %d at time %d ", gnt1,$time);

25
      end    

26
      default: begin

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         state <= #1 next_state;

28
         state <= IDLE;

29
      end

30
     endcase

31
   end

32
 end
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