`timescale 1ns/1ns 
module tb_arbiter;
 reg req0=0;
 reg req1=0;
 wire gnt0;
 wire gnt1;
 reg clk=0;
 reg reset =0;

arbiter3 a1(.req0(req0), .req1(req1), .gnt0(gnt0), 
	.gnt1(gnt1),.clk(clk), .reset(reset));

 always #5 clk=~clk;
 initial
 begin
	 #200 $finish;
 end
 initial
 begin
	 $dumpfile("output.vcd");
	 $dumpvars;
	#10 req1 = 1;
	#20 req1 = 0;
	#10 req0 = 1;
	#10 req0 = 0;
        #10 req1 = 0;
	//#20 req0 = 1; req1=0;
	//#20 req0 = 0;
 end 

 initial
 begin
	 reset = 1;
	 #9 reset = 0;
	 //#70 reset = 1;
	 //#20 reset = 0;
 end
endmodule


module arbiter (req0,
		req1,
		gnt0,
		gnt1,
		clk,
		reset);
	input req0,req1;
	input clk, reset;
	output reg gnt0, gnt1;
	reg[1:0] state;

	parameter IDLE = 0;
	parameter GNT0 = 1;
	parameter GNT1 = 2;

	always @(posedge clk)
	begin: FIRST_ARBITER
		if (reset) 
		begin
			gnt1 <= #1 0;
			gnt0 <= #1 0;
			state <= #1 IDLE;
		end else case (state)
			IDLE:
			begin
				if (req0) 
				begin
					state <= #1 GNT0;
					gnt0 <= #1 1;
				end else if (req1)
				begin
					gnt1 <=#1 1;
					state <= #1 GNT1;
				end else begin
					gnt0<=#1 0;
					gnt1<=#1 0;
					state <= #1 IDLE;
				end
			end

			GNT0:
			begin
				if (req0) begin
					gnt0 <=#1 1;
					state <=#1 GNT0;
				end else begin
					gnt1 <=#1 0;
					state <=#1 IDLE;
				end
			end

			GNT1:
			begin
				if (req1) begin
					state <= #1 GNT1;
				end else begin
					gnt1 <=#1 0; 
					state <= #1 IDLE;
				end
			end
			//default: state <= #1 state;
			default:
				state = IDLE;
		endcase


	end

	always @(posedge clk)
	begin
		if (state == IDLE) begin
			$display(" state is IDLE  %d \n", state);
		end else if (state == GNT0) begin
			$display(" state is GNT0 %d \n", state);
		end else begin
			$display(" state is GNT1 %d \n", state);
		end

	end
endmodule

module arbiter2 ( req0, req1, gnt0, gnt1, reset, clk);
input req0, req1, reset, clk;
output reg gnt0, gnt1;

 always @(posedge clk)
 begin: SECOND_ARBITER
	if (reset) begin
		gnt0 <= #1 0;
		gnt1 <= #1 0;
	end else if (req0 == 1 && req1 == 1) begin
		gnt0 <= #1 1;
		gnt1 <= #1 0;
	end else if (req0 == 0 && req1 == 1 ) begin
		gnt0 <= #1 0;
		gnt1 <= #1 1;
	end else if (req0 == 0 && req1 == 0 ) begin
		gnt0 <= #1 0;
		gnt1 <= #1 0;
	end else begin
		gnt0 <= #1 1;
		gnt1 <= #1 0;
	end
 end
endmodule

module arbiter3( req0, req1, reset, clk, gnt0, gnt1);
input req0, req1,reset, clk;
output reg gnt0, gnt1;
reg [1:0] next_state, state;

 parameter IDLE=0;
 parameter GNT0=1;
 parameter GNT1=2;

 always @(state, req0, req1)
 begin : COMB_LOGIC
	 next_state = IDLE;
	 case (state)
	 IDLE: if (req0 == 1 ) begin
	  	 next_state = GNT0;
		 //gnt0 = 1;
	   end else if (req1==1) begin
		 next_state = GNT1;
		 //gnt1 = 1;
	   end else begin
		 next_state = IDLE;
	   end
	 GNT0: if (req0 == 1)
		   next_state = GNT0;
	      else begin
		   next_state = IDLE;
	   end

	   GNT1: if (req1 ==1) begin
		   next_state = GNT1;
	   end else begin
		   next_state = IDLE;
	   end

	 default:
		next_state = IDLE; 
	 endcase
 end

 always @(posedge clk) 
 begin : OUTPUT_LOGIC
	 if (reset) begin
		 gnt0 <= #1 0;
		 gnt1 <= #1 0;
		 state <= #1 IDLE;
	 end else begin
		 $monitor(" time for state assignment %d is %d \n",state, $time);
		 case (state)
			 IDLE: begin
				 $display("set both gnt0 and gnt1 0");
		 		 state <= #1 next_state;
				 gnt0<=  #1 0;
		       		 gnt1<=  #1 0;
			 end
			 GNT0: begin
				 gnt0 <= #1 1;
		 		 state <= #1 next_state;
			 end
			 GNT1: begin
				$display(" time for gnt1 assertion is %d ", $time); 
			 	gnt1 <= #1 1;
		 		state <= #1 next_state;
				$display(" gnt1 is %d at time %d ", gnt1,$time);
			end		
			default: begin
		 		state <= #1 next_state;
		 		state <= IDLE;
			end
		 endcase
	 end
 end
endmodule

module test(input a, b,c,d,e,
	output reg y);
	always @(*)
	begin
		y<=a;
		if (b)
			y= #1 c;
		if (d)
			y= #1 e;
	end

endmodule