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Forum: FPGA, VHDL & Verilog VHDL Double and Single clocks designs compare


von Alexander S. (Company: Home) (alex_isr)


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Attached ModelSim and Vivado VHDL design of two way implementation of 7 
consecutive transactions : one by single clock and second by 2 clocks : 
Clock and not Clock.
 In the pictures we can see that with same size of hardware second way 
(2 clocks) more quickly : see signals sClockData(single clock disign) 
and dClockData(Double Clocks design) calculated from same DataIn.
 So, by using two clocks : Clock and not Clock you can make part or all 
your design more quickly or use more slow clock.

 Regards Alex.

 P.S.

Clock and not Clock you can generate by FPGA PLL.

Regards Alex.

: Edited by User
von -gb- (Guest)


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The Logic between the clock edges determines the maximum speed. So if 
you have leisure time between the edges simply incease your clock speed. 
Much simpler than to introduce a second clock.

von daniel__m (Guest)


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Alexander S. wrote:
> So, by using two clocks : Clock and not Clock you can make part or all
> your design more quickly

That's right, your design will be faster in terms of latency. And right, 
you have 2 (slow) clocks. Buts clocks are (almost) never the problem. 
The problem is the propagation delay between 2 synchronous elements (eg. 
ff). You have halfed the time, which is effectively the same as using 
one clock with doubled frequency. That's your speed benefit.

greetings

von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
> So, by using two clocks : Clock and not Clock you can make part or all
> your design more quickly or use more slow clock.
Despite the https://embdev.net/topic/498573#6311869 you don't get the 
trick at all, do you?

One very last try...

Lets look at this usual FPGA structure (every FPGA or logic design in 
general is similar to this):
      tsu=1ns
        tco=1ns
          ----             ----             ----             ----                 
     ...-|D  Q|-- logic --|D  Q|-- logic --|D  Q|-- logic --|D  Q|-... 
         |    |  tpd=8ns  |    |    5ns    |    |    10ns   |    |               
         |    |           |    |           |    |           |    |               
       .-|>   |         .-|>   |         .-|>   |         .-|>   |           
       |  ----          |  ----          |  ----          |  ----          
clk  --o----------------o----------------o----------------o-------...
How fast can the clk frequency be here?
Its very simple to calculate: 1/(tpdmax+tsu+tco) = 1/12ns = 83MHz

And now its your turn:
      tsu=1ns
        tco=1ns
          ----             ----             ----             ----                 
     ...-|D  Q|-- logic --|D  Q|-- logic --|D  Q|-- logic --|D  Q|-... 
         |    |  tpd=8ns  |    |    5ns    |    |    10ns   |    |               
         |    |           |    |           |    |           |    |               
       .-|>   |         .-|>   |         .-|>   |         .-|>   |           
       |  ----          |  ----          |  ----          |  ----          
clk  --o----------------+----------------o----------------+-------...
                        |                                 | 
nclk -------------------o---------------------------------o-------...
How fast can the clk frequency be here?

von Alexander S. (Company: Home) (alex_isr)


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daniel__m wrote:
> Alexander S. wrote:
>> So, by using two clocks : Clock and not Clock you can make part or all
>> your design more quickly
>
> That's right, your design will be faster in terms of latency. And right,
> you have 2 (slow) clocks. Buts clocks are (almost) never the problem.
> The problem is the propagation delay between 2 synchronous elements (eg.
> ff). You have halfed the time, which is effectively the same as using
> one clock with doubled frequency. That's your speed benefit.
>
> greetings

 You are right for max. system frequency and this max system frequency 
for big designs you can implement only by synchronous design.

 My test say : for same system (not. max. FPGA frequency ) frequency 
using two clocks : Clock and not clock make you design more quickly such 
as design x 2 frequency.

 Regards Alex.

von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:

> How fast can the clk frequency be here?

  If my system work by Clock and not Clock such as 10 MHz for release 
same function by single clock system you need work with system clock 20 
MHz.

 That you can see on the picture.

 Regards Alex.

von Alexander S. (Company: Home) (alex_isr)


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Question to Moderator : why impossible to edit posts after some minutes 
after posting ?


 Regards Alex.

von Christoph Z. (christophz)


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Alexander S. wrote:
> If my system work by Clock and not Clock such as 10 MHz for release
> same function by single clock system you need work with system clock 20
> MHz.
>
>  That you can see on the picture.

This is correct. But in both cases you need an FPGA technology that is 
fast enough to get the work done in 1/20 MHz = 50 ns.

If you would argue with power consumption that with two clocks only half 
the registers toggle at the same time then it would be a different 
discussion. Intel is still using a lot two phase clocking scheme in 
their processors. But it's one of few companies still using it, building 
the clock tree is much more work than with a single one.

von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
> If my system work by Clock and not Clock such as 10 MHz for release same
> function by single clock system you need work with system clock 20 MHz.
And having a view at this FSM template 
https://embdev.net/topic/498573#6310299 it results in something like 
this:
      tsu=1ns
        tco=1ns
          ----           ----       ----             ----       ----                
  ...----|D  Q|- logic -|D  Q|-----|D  Q|-- logic --|D  Q|-----|D  Q|-
         |    |   8ns   |    | 1ns |    |    10ns   |    | 1ns |    |              
         |    |         |    |     |    |           |    |     |    |    
       .-|>   |       .-|>   |   .-|>   |         .-|>   |   .-|>   |            
       |  ----        |  ----    |  ----          |  ----    |  ----      
clk  --o--------------+----------o----------------+----------o--------...
                      |                           | 
nclk -----------------o---------------------------o-------------------...
There's only routing delay between the falling edge FF and the rising 
edge FF.
How fast is this design? Whats the advantage to do it this way?
Is ist faster than the one without the falling edge clock?


Christoph Z. wrote:
> If you would argue with power consumption that with two clocks only half
> the registers toggle at the same time then it would be a different
> discussion.
There is no change in the power demands mean value. Its just a half of 
simultaneous switching FF and therefore a reduction of ground 
bouncing/noise inside the silicon.

: Edited by Moderator
von Alexander S. (Company: Home) (alex_isr)


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Christoph Z. wrote:
 Intel is still using a lot two phase clocking scheme in
> their processors. But it's one of few companies still using it

But it's one of biggest company in the world !

 Regards Alex.

 P.S.

 In my FPGA I try to use system clock slowest as possible and this way 
is help me.

I try to design only synchronous VHDL components with only synchronous 
reset ready to high speed as possible ... with clock slow as possible .

 For me it's good practice design rules.

 Regards Alex.

von Alexander S. (Company: Home) (alex_isr)


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Christoph Z. wrote:

> If you would argue with power consumption that with two clocks only half
> the registers toggle at the same time

with slow (half) clock. So , it may be quarter power ?

 Other question if you need only small part of design quickly : you 
other slow part of design work with slow clock.

So, if only small part of your design must work with max. speed such as 
400 MH ... biggest part of your design may work 200 MHz it's other kind 
of high speed design.

 Regards Alex

von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:

> How fast is this design?

 With same clock (not max.high speed of FPGA less than ~100 MHz) double 
clock design is faster functionaly and we see that in the picture !

 Regards Alex.

P.S.

 Design function released with one clock 100 MHz
can be implemented by double clock design technology with system clock 
50 MHz. Sometimes it's important and preferred.

von Lothar M. (lkmiller) (Moderator)


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Alexander S. wrote:
> Design function released with one clock 100 MHz can be implemented by
> double clock design technology with system clock 50 MHz.
Only when logic is balanced also.

But not with your FSM template.
Because with that "double-edge-clock" design like in 
https://embdev.net/topic/498784#6314618 the high time of the clock 
must be 12ns. And if it is a 50:50 clock, then the low time of the 
clock is also 12ns. And 1/(12ns+12ns) is 41,6 MHz.
And now it comes: during the low time of the clock cycle nothing is 
calculated or done, because there is only a wire between die falling 
edge FF and the rising edge FF. And when nothing is done, then time is 
lost.

It is simply that way. Think about it until you understand it.

von Alexander S. (Company: Home) (alex_isr)


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Lothar M. wrote:
> Alexander S. wrote:

> But not with your FSM template.

 My tempate of State Machin with double clock have same functional speed 
as state machin with one clock.

 I use not Clock sygnal for implement synchronous next state logic.
By definition synchronous logic more quikly then asynchronous.
 So, state machin will can work with higher clock.

 I also use synchronous next state output logic for State Machine output 
logic generation signal.

 Regards Alex.

: Edited by User

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