VHDL WatchDog/(One-Shot)

Alexander S. wrote:
> Attached ModelSim VHDL design of WatchDog
Pls attach the VHDL source file as a *.vhd or *.vhdl file. Then it can 
be read witout unpacking on mobile devices also.

Pls attach the VHDL : See attached files.

Duke Scarring wrote:
> Alexander S. wrote:
>> See attached files.
> Thanks.
>
> Using both clock edges in a design is calling for trouble. In your
> watchdog design it is absolutley not necessary:
>

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> process (ClockIn)

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> begin

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> if ClockIn'event and ClockIn = '0' then

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> ...

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>  RequestRise_Process:

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> process (ClockIn)

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> begin

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>  if(ClockIn'event and ClockIn = '1') then

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>

> Duke

 You're right .

 It's my old design.

 Flip Flops does not work by clock's Fall  , synthesis tools must add 
some components for invert clock.

 See attached design after repair.

 Regards Alex.