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Forum: FPGA, VHDL & Verilog VHDL WatchDog/(One-Shot)


VHDL WatchDog/(One-Shot)
von Alexander S. (Company: Home) (alex_isr)

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Attached ModelSim VHDL design of WatchDog/(One-Shot).

Regards Alex.

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Re: VHDL WatchDog/(One-Shot)
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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Alexander S. wrote:
> Attached ModelSim VHDL design of WatchDog
Pls attach the VHDL source file as a *.vhd or *.vhdl file. Then it can 
be read witout unpacking on mobile devices also.

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Re: VHDL WatchDog/(One-Shot)
von Alexander S. (Company: Home) (alex_isr)

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Pls attach the VHDL : See attached files.

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Re: VHDL WatchDog/(One-Shot)
von Duke Scarring (Guest)

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Alexander S. wrote:
> See attached files.
Thanks.

Using both clock edges in a design is calling for trouble. In your 
watchdog design it is absolutley not necessary:
1
process (ClockIn)

2
begin

3
if ClockIn'event and ClockIn = '0' then

4
...

5
 RequestRise_Process:

6
process (ClockIn)

7
begin

8
 if(ClockIn'event and ClockIn = '1') then


I prefer maximum readability of vhdl sources, so I use more indentation 
an rising_edge() for clocks.

Duke

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Re: VHDL WatchDog/(One-Shot)
von Alexander S. (Company: Home) (alex_isr)

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Duke Scarring wrote:
> Alexander S. wrote:
>> See attached files.
> Thanks.
>
> Using both clock edges in a design is calling for trouble. In your
> watchdog design it is absolutley not necessary:
>
1
> process (ClockIn)

2
> begin

3
> if ClockIn'event and ClockIn = '0' then

4
> ...

5
>  RequestRise_Process:

6
> process (ClockIn)

7
> begin

8
>  if(ClockIn'event and ClockIn = '1') then

9
>

> Duke

 You're right .

 It's my old design.

 Flip Flops does not work by clock's Fall  , synthesis tools must add 
some components for invert clock.

 See attached design after repair.

 Regards Alex.

: Edited by User
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