VHDL WatchDog/(One-Shot)Attached ModelSim VHDL design of WatchDog/(One-Shot). Regards Alex.
Attached files:
Alexander S. wrote: > Attached ModelSim VHDL design of WatchDog Pls attach the VHDL source file as a *.vhd or *.vhdl file. Then it can be read witout unpacking on mobile devices also. Pls attach the VHDL : See attached files.
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Alexander S. wrote: > See attached files. Thanks. Using both clock edges in a design is calling for trouble. In your watchdog design it is absolutley not necessary:
I prefer maximum readability of vhdl sources, so I use more indentation an rising_edge() for clocks. Duke Duke Scarring wrote: > Alexander S. wrote: >> See attached files. > Thanks. > > Using both clock edges in a design is calling for trouble. In your > watchdog design it is absolutley not necessary: >
> Duke
You're right .
It's my old design.
Flip Flops does not work by clock's Fall , synthesis tools must add
some components for invert clock.
See attached design after repair.
Regards Alex.
Attached files:
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