-------------------------------------------------------------------------------- -- -- Title : Scanner FPGA -- Design : Rise and Fall pulse -- Author : Alex Shtengel -- Company : Lumenis -------------------------------------------------------------------------------- -- File : DigDef.vhd -- Generated : Mar 15 2015 -------------------------------------------------------------------------------- -- Description : Generate Rise and Fall pulse -------------------------------------------------------------------------------- -- Revision History : -- ----------------------------------------------------------------------------- -- Ver :| Author :| Mod. Date :| Changes Made: -- v1.0 | Alex Shtengel :| 15/03/15 :| Automatically Generated -- ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity DigDef is port ( ClockIn, nClockIn, nResetIn, InputSignal : in std_logic; RiseOutput, FallOutput : out std_logic ); end DigDef; architecture aDigDef of DigDef is signal InputSignalF,InputSignalFf : std_logic := '0'; signal nInputSignalF,nInputSignalFf : std_logic := '1'; begin PipeLine: process (ClockIn) begin if(ClockIn'event and ClockIn = '1') then case nResetIn is when '0' => InputSignalF <= '0'; InputSignalFf <= '0'; nInputSignalF <= '1'; nInputSignalFf <= '1'; when others => InputSignalF <= InputSignal ; InputSignalFf <= InputSignalf ; nInputSignalF <= not InputSignal ; nInputSignalFf <= nInputSignalF ; end case; end if; end process PipeLine; OutProcess: process(nClockIn) begin if (nClockIn'event and nClockIn = '1') then case nResetIn is when '0' => RiseOutput <= '0'; FallOutput <= '0'; when others => RiseOutput <= InputSignalF and ( not InputSignalFf ); FallOutput <= nInputSignalF and ( not nInputSignalFf ); end case; end if; end process OutProcess; end aDigDef;