Hi all,
found my self using the SPI slave description from the link bellow
(sorry for not making it an actual link)
Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?"
I have reached the point now that it is fully working on HW, with a
system clock of 100MHz, sampling a serial clock of 18,75MHz.
But i had to add a line of code and wanted some feedback or your
thoughts about it. Maybe someone else needs this fix (?).
First of all, i tried both iterations, as shown bellow:
1 | MISO <= dsr(dsr'left) when SSn='0' else 'Z'; -- Richtungsteuerung MISO direkt über SSn
|
2 | MISO <= misoLoc when SSn='0' else 'Z'; -- Richtungsteuerung MISO direkt über SSn
|
Without the use of misoLoc signal, my simulations resulted in one bit
shift on all Master received data.
With the use of the misoLoc signal, my simulations looked absolutely
fine, but when tried on HW, found a one bit error, MSB which is
transmitted first.
I then managed to reproduce the one bit error in simulations also.
Then i could actually analyse it much better. What I saw (which is also
seen on the simulations of the original post), is that the misoLoc
signal, got its value from the received 16-bit word, and not from the
next word we want to transmit.
It did not take too long to see the fix. The state of the misoLoc signal
is never set during NOT chip selected. It always gets the MSB of dsr
when sclkSR="10".
So my simple fix is shown bellow:
1 | -- Parallel-Eingänge --> MISO
|
2 | process begin
|
3 | wait until rising_edge(clk);
|
4 | if (ssSR="11") then -- solange deselektiert: immer Daten vom Din übernehmen
|
5 | dsr <= Din;
|
6 | misoLoc <= Din(15);--**MISSING BIT FIX**
|
7 | elsif (sclkSR="01") then -- mit der steigenden SCLK-Flanke
|
8 | dsr <= dsr(dsr'left-1 downto 0) & MOSI; -- wird MOSI eingetaktet
|
9 | end if;
|
10 | if ( sclkSR="10" ) then -- mit der fallenden Flanke an MISO ausgeben
|
11 | misoLoc <= dsr(dsr'left);
|
12 | end if;
|
13 | end process;
|
14 |
|
15 | MISO <= misoLoc when SSn='0' else 'Z'; -- Richtungsteuerung MISO direkt über SSn
|
Since data to be transmitted must be ready when NOT chip selected, we
can use the MSB to set the correct level to the internal signal. After
that, things just work!
What do you think?
Watch this topic
Disable multi-page view