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Forum: FPGA, VHDL & Verilog Comments on: Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?"


Author: SparkyT (Guest)
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Hi all,
found my self using the SPI slave description from the link bellow
(sorry for not making it an actual link)

Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?"

I have reached the point now that it is fully working on HW, with a 
system clock of 100MHz, sampling a serial clock of 18,75MHz.
But i had to add a line of code and wanted some feedback or your 
thoughts about it. Maybe someone else needs this fix (?).
First of all, i tried both iterations, as shown bellow:
  MISO <= dsr(dsr'left) when SSn='0' else 'Z';  -- Richtungsteuerung MISO direkt über SSn
  MISO <= misoLoc when SSn='0' else 'Z';  -- Richtungsteuerung MISO direkt über SSn

Without the use of misoLoc signal, my simulations resulted in one bit 
shift on all Master received data.
With the use of the misoLoc signal, my simulations looked absolutely 
fine, but when tried on HW, found a one bit error, MSB which is 
transmitted first.
I then managed to reproduce the one bit error in simulations also.
Then i could actually analyse it much better. What I saw (which is also 
seen on the simulations of the original post), is that the misoLoc 
signal, got its value from the received 16-bit word, and not from the 
next word we want to transmit.
It did not take too long to see the fix. The state of the misoLoc signal 
is never set during NOT chip selected. It always gets the MSB of dsr 
when sclkSR="10".
So my simple fix is shown bellow:

  -- Parallel-Eingänge --> MISO
  process begin
     wait until rising_edge(clk);
     if (ssSR="11") then                        -- solange deselektiert: immer Daten vom Din übernehmen
        dsr <= Din;
        misoLoc <= Din(15);--**MISSING BIT FIX**
     elsif (sclkSR="01") then                   -- mit der steigenden SCLK-Flanke 
        dsr <= dsr(dsr'left-1 downto 0) & MOSI; -- wird MOSI eingetaktet
     end if;
   if ( sclkSR="10" ) then -- mit der fallenden Flanke an MISO ausgeben
    misoLoc <= dsr(dsr'left);
   end if;
  end process;

 MISO <= misoLoc when SSn='0' else 'Z';  -- Richtungsteuerung MISO direkt über SSn

Since data to be transmitted must be ready when NOT chip selected, we 
can use the MSB to set the correct level to the internal signal. After 
that, things just work!

What do you think?

: Edited by Moderator
Author: Lothar M. (lkmiller) (Moderator)
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SparkyT wrote:
> is that the misoLoc signal, got its value from the received 16-bit
> word, and not from the next word we want to transmit.
> ...
> What do you think?
Sounds somewhat like "wrong SPI mode" to me...


> (sorry for not making it an actual link)
I corrected that.
Simply copy the link into the text box as in the screenshot...

: Edited by Moderator
Author: SparkyT (Guest)
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Thanks for the link correction.

Lothar M. wrote:
> Sounds somewhat like "wrong SPI mode" to me...

If it was a wrong SPI mode, the master would not read anything.
Correct?

I have attached the simulation of the original post, with a marker.
You can clearly see the state of the MISO internal signal change, and 
carried over to the next transmission.
Its the double registering of the SCLK that pushes a new level onto the 
MISO internal signal.
So my fix, simply sets it to what it is supposed to be, rather than to 
what was received.

Author: Lothar M. (lkmiller) (Moderator)
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SparkyT wrote:
> If it was a wrong SPI mode, the master would not read anything. Correct?
It would be "shiftet" one bit to left or right. Exactly as you have 
it...

With my code in Beitrag "Re: Erfahrung mit SPI Slave und Spartan 6 FPGA?" 
data is changed a the rising edge of SCLK and it is latched at the 
falling edge. As CPOL is low the first rising edge of SCLK in a trlegram 
causes MISO to be updated with the desired and necessary value.
According to http://www.lothar-miller.de/s9y/uploads/Bilder/SPI.pdf
this is SPI mode 1 with CPOL = 0 and CPHA = 1

In your waveform I cannot dig out, what SPI mode you want to use. The 
timing for MOSI and MISO does not fit together...

: Edited by Moderator
Author: SparkyT (Guest)
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Lothar M. wrote:
> According to http://www.lothar-miller.de/s9y/uploads/Bilder/SPI.pdf
> this is SPI mode 1 with CPOL = 0 and CPHA = 1
You are on to something there...

Lothar M. wrote:
> I cannot dig out, what SPI mode you want to use
Looks like me neither...

I see now the bit shift, what it means. got your code now working, no 
misoLoc signal.

Master (testbench) Shifts MOSI on risedge, and samples MISO on falledge
slave  samples MOSI (and shifts MISO) on double registered fall edge

Here is a post layout simulation. Testbench catches (and pushes) top 
level signals.  The slave must reply with x"0100" and read x"0111".

I had wrong modes as you said. But using the misoloc, added delays, and 
made it work, i think(?). Now its properly set-up, i hope.

I will come back with hw confirmation. I think am getting there.
Thanks for the feedback

Author: SparkyT (Guest)
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Working on hw as expected.
Thanks for the feedback.
Might i suggest to rename the post to,

''What does a bit shift mean?''

out of respect for that beautiful spi slave description.

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