Hello. I have to do a project which will be a simulator of 16 bit FIFO memory in VHDL. I need to add values to my memory and later put it on 7-segment display, but I don't even know how to deal with it. Can you give me some advice how can I do this project? I know these things: * I need read flag on slider * I need write flag on slider * I need input logic_vector 15 downto 0 and pin it to sliders * I need output logic_vector 15 downto 0 and then via component push it to display (not sure here) * clk on button for example to send my value to memory I don't know how I can store my data in "memory" and I'm bad in understand components. I'm not sure how to write it "not structural" I mean I want write it in multiple files not only in one file, but I have problems with send component from file to my top entity
This obviously is some kind of homework. Your teacher wants you to do something and learn by doing that. We should not override this intention. So let's try it this way: you start with something and we help you on particular questions. First you will need a VHDL module with the mentioned ports. In that module you will need a array to store the incoming data. And you will need two pointers, one for the write position and one for the read position. This module will also need a clock to handle the pointers. Additionally you will need a VHDL module to handle the button and one VHDL module to handle the display. BTW: it would be very neat to have a flag showing that there's data stored in the fifo at all. Otherwise you could read the fifo without having written data in it...
It's project for end the semester. I'm trying to do it alone, but I have some problems and no time to go to the teacher for resolve that problems, because I'm working in the middle of week. I did in other files connected 2 7-segments displays. That was the easiest part of project. In another file I did entity which tries store data, but I can't find how to write my vector to variable and then change it again for bytes. Unfortunately, I don't have FPGA to test my project. Now I'm trying do these pointers, but if I have pointers must I save my last positions? I will think how to do it, but it help me a bit. Still I can't connect these files. I mean everything works not connected like another projects, because I have problem with add it to top entity in my main project.
In your Top-Level File you put a Component Part in the Architecture Section.
ARCHITECTURE bdf_type OF Block_toplevel IS component quad is port( clk : in std_logic; reset_n : in std_logic; quadA : in std_logic; quadB : in std_logic; count : out std_logic_vector(23 downto 0) ); end component; BEGIN -- ------------------------------------------------------------------------ -- Panasonic Rotary-Encoder -- quad1 : quad PORT MAP ( clk => hw_clk, reset_n => hw_reset, -- quadA => Q1_debouced, -- quadB => Q2_debouced, quadA => Q1, quadB => Q2, -- count => s_quad1_out count => s_addr_i ); ... END bdf_type;
left-side is the Entity Part, right side are signals or connections to yout Hardware .
The File with the "Quad" Part schould be also in your Project.
Patryk S. wrote: > Unfortunately, I don't have FPGA to test my project. first the whole thing must run properly in simulation. And be happy: because the buffer is so small (only 16 words) you will be able to use distributed RAM instead of invoking a RAM block. > Now I'm trying do these pointers, but if I have pointers must I save my > last positions? Have a lok at this: http://www.lothar-miller.de/s9y/archives/21-FIFO.html Its German, but when you (try to) understand the (faily simple and straight forward) code, then you will get the trick. Patryk S. wrote: > * clk on button Usually a very, very bad idea. This will only work when you have a properly debounced button... Marek wrote: > The File with the "Quad" Part schould be also in your Project. Wrong thread? I cannot see any need for a rotary encoder here.
Patryk S. wrote: > I want write it in multiple files not only in one file, but I have > problems with send component from file to my top entity Ich dachte er hat Probleme die Komponenten zu verbinden. Oder habe ich was falsch verstanden? mfg
Marek wrote: > Oder habe ich was falsch verstanden? Pls. write in English. Keep in mind EmbDev.net is the English spoken part of https://www.mikrocontroller.net/ Patryk S. wrote: > Still I can't connect these files. You have problems with the instantiation of one or multiple components in a VHDL module? If so, then read on, otherwise skip to the next post... ;-) Its the very same like instantiating a module into a test bench (eg. like the decoder in the test bench ther in the https://embdev.net/topic/465973#5685466) Afterwards you will have to connect those modules with internal signals. There I'm taking a DDFS module and a PWM module and connect them together to generate a sine modulated PWM output: http://www.lothar-miller.de/s9y/archives/57-Sinusausgabe-mit-PWM.html Its German, but I'm sure you will get the trick...
Lothar M. wrote: > Pls. write in English. You are right. I schould read more carefully before i write. mfg
You help me so much. I understand a bit deutch so I hadn't problem with that code. I resolve most of my problems. Now I have one problem with simulator. I use altera modelsim and I don't know how to set manualy without code specified value. For example I have input A and B and now I want set on A 0 and on B 1. How can I do it without write it in code? EDIT: Ohh okay. I realize how to do it. I can force it. This video help me do it. (https://www.youtube.com/watch?v=W9rANBbhbSo) Most difficult part of coding it for me is change my 1 big file to many small others. I changed 2 of my 10 components, but I lost for it a couple hours. I don't understand signals in my code. That testbench. I saw that testbench. Can I join it outside my project? I tried, but I didn't knew how to pin it properly
: Edited by User
Patryk S. wrote: > How can I do it without write it in code? Don't know that tool. But I never ever did something with that "forcing" in a simulator, because simulation is not a real-time story. So there is no need for a "button" to force signals to a certain value. A test bench simply should invoke the possible usual input stimuli to a module, and then it should add some "errouneous" input states to check how the module handles problems and recovers from them. And because its best to have alwas the very same timing throughout test, its best to write it in a file to have the very same conditions throughout development. > That testbench. I saw that testbench. Can I join it outside my project? A test bench is a stimlui file that is not inside the final hardware files. It is solely for simulation and invokes the "module under test" as a component. So in HDL development you have 2 "projects": 1. the one that will be synthesized and implemented on on real hardware and 2. that one for simulation. It is a test bench which includes one or more of the modules from the 1. project. You also can have multiple test benches e.g. each one for the each sub module (debouncer, encoder, decoder, somewhatelse...) and also maybe one "big" test bench for the top level module of the design.
: Edited by Moderator
Still I have problem with components. How Can I pin it? I will send example for my top entity and component which I want to use
Library IEEE; USE IEEE.Std_logic_1164.all; use IEEE.NUMERIC_STD.ALL; entity fifo_memory is port ( data_in: in std_logic_vector(memory_architecture-1 downto 0); -- data input. Value which will be put into our memory read_flag: in std_logic; -- read flag write_flag: in std_logic; -- write flag clk: in std_logic; -- not sure to use action_button: in std_logic; -- master button data_out: out std_logic_vector(memory_architecture-1 downto 0) -- data output. Value which will be throw by our memory. This one will be converted to our 7-seg display ); end fifo_memory; architecture Behavioral of fifo_memory is --code signal f_led_out : std_logic_vector(6 downto 0); component bcd_flag is port ( f_led_out: out std_logic_vector(6 downto 0) ); end component; begin bcd_flag_component: bcd_flag PORT MAP( f_led_out => f_led_out ); --code flagBCD: process(read_flag, write_flag) begin if (read_flag='1' and write_flag='0') then f_led_out <= "1001111"; -- I end if; if (read_flag='0' and write_flag='1') then f_led_out <= "0000001"; -- O end if; if (read_flag='1' and write_flag='1') then f_led_out <= "0110000"; -- E end if; end process flagBCD; end Behavioral;
Error (12006): Node instance "bcd_flag_component" instantiates undefined entity "bcd_flag". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
I have problem with this error. I surrender with push it to multpile files and I try do it in one, but I can't pin new components
Patryk S. wrote: > Node instance "bcd_flag_component" instantiates undefined entity > "bcd_flag". You must include the module bcd_flag into your project.
I understood error and even I tried to do it in some ways, but I don't know how to use component in component. I don't know how to include this module. I want to have some variables as component and from other component push it to this component. I tried to do it in a new file, but I don't know how to do it. Once I ran my program properly, but I couldn't simulate my program and I had warning design connected with this f_led_out in the console EDIT: I appreciate some help. I fight with this last 2 days :( EDIT2: I might say nosense, but I want send data from my component/entity called fifo_memory to my component bcd_flag. Something like it's written in code. I cut everything what I thought isn't needed here. I'm trying cut everything from fifo_memory to another components, coz I wanted to do it on multiple files or even in one file, but with component. It's required in project
: Edited by User
I have last question. How Can I add std_vector to std_vector? I want do something like this
d_units <= std_logic_vector((d_value mod 10)); d_tens <= std_logic_vector(((d_value / 10) mod 10));
I create it as std_logic_vector, but I can't assign math operations
Patryk S. wrote: > I create it as std_logic_vector, but I can't assign math operations A std_logic_vector is just a bunch of bits, so it is not a good idea to perform on it. Does it represent a signed or is it unsigned or even a float number? How should the synthesizer know? You could use the old-fashioned std_logic_arith package to do so, but much better is to use the numeric_std package and to cast the std_logic_vector to a defined unsigned or signed data type: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std > (d_value mod 10) > ((d_value / 10) mod 10) A division in hardware is a fairly demanding task. Much more when its done in pure logic as you want the synthesizer to do here. What are those two results needed for?
: Edited by Moderator
It looks like a Hex to dec converter. This need a division unit. It is not possible to calculate this in on clock cycle or only with an assign.
René D. wrote: > It is not possible to calculate this in on clock cycle or only with an > assign. Depends on the toolchain... ;-) See Beitrag "Re: Rechnen mit unsigned vs. signed und einer division" (its German, but maybe Google translates it). But indeed such a combinatorial divider needs a big bunch of logic gates and it is slow. > It looks like a Hex to dec converter A binary to BCD converter can be done like this: http://www.lothar-miller.de/s9y/archives/67-Vektor-nach-BCD-kombinatorisch.html Or this: http://www.lothar-miller.de/s9y/archives/34-Vektor-nach-BCD.html Or much better like this: http://www.lothar-miller.de/s9y/archives/84-Binaer-nach-BCD-mit-1-Takt-pro-Stelle.html