hi, i wrote i code for a 3 to 8 decoder in modelsim and it dosent work proprly in the simulation. when i force "000" it works, meaning the output is "10000000" and also it works with "001" that gives the output "01000000". but the other inputs give those same outputs over and over agian. not only that, but when i force "010" in the input it enters "000" in the input for some reason. code:

library ieee; use ieee.std_logic_1164.all; entity Decoder is port ( a : in std_logic_vector (2 downto 0); en : in std_logic; f : out std_logic_vector (7 downto 0) ); end Decoder; architecture bhv of Decoder is begin process (en,a) begin if en = '1' then if a="000" then f<="10000000" after 1 ps; elsif a="001" then f<="01000000" after 1 ps; elsif a="010" then f<="00100000" after 1 ps; elsif a="011" then f<="00010000" after 1 ps; elsif a="100" then f<="00001000" after 1 ps; elsif a="101" then f<="00000100" after 1 ps; elsif a="110" then f<="00000010" after 1 ps; elsif a="111" then f<="00000001" after 1 ps; else null; end if; end if; end process; end bhv; |

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Edited by Moderator

ee_vhdl wrote: > when i force "000" > ... > but when i force "010" Why don't you simply write a test bench with 20 lines of code? Then you will not need that questionable "force"-construct. ee_vhdl wrote: > else null; You know that a) you are bulding a latch with this or b) this line is absolutely useless?

what do you mean about the 20 line code? i have a project that a decoder is just one of the components, i need to shoe the prop' that the decoder works inside the simulation. why is the null useless?

ee_vhdl wrote: > i have a project that a decoder is just one of the components, i need > to shoe the prop' that the decoder works inside the simulation. So write a test bench for that single component "decoder". > what do you mean about the 20 line code? That testbench will be not much longer than 20 lines of VHDL code. > why is the null useless? In which case could it be usefull? How could that case happen? I would write the last lines if that if-elsif-query like that:

elsif a="110" then f<="00000010" after 1 ps; else f<="00000001" after 1 ps; end if; |

```
> after 1 ps;
My hint here: do not use symbolic delays in a behavioural description.
You may encounter curious effects now and then...
```

Lothar M. wrote: > That testbench will be not much longer than 20 lines of VHDL code. Ok, skipping some blank lines...

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY tb_decoder IS END tb_decoder; ARCHITECTURE behavior OF tb_decoder IS COMPONENT Decoder PORT( a : IN std_logic_vector(2 downto 0); en : IN std_logic; f : OUT std_logic_vector(7 downto 0)); END COMPONENT; signal a : std_logic_vector(2 downto 0) := (others => '0'); signal en : std_logic := '1'; signal f : std_logic_vector(7 downto 0); BEGIN uut: Decoder PORT MAP ( a => a, en => en, f => f); a <= "000" after 0ns, "001" after 10ns, "010" after 20ns, "011" after 30ns, "100" after 40ns, "101" after 50ns, "110" after 60ns, "111" after 70ns; END; |

Simulation result: your decoder looks fine. See the attached WF_decoder_1.png BUT... there are latches in the desgign: when en='0' then the last result is stored (WF_decoder_2.png). Thats not the usual behaviour for such a device. I would change the code in a way that the result is "00000000" when en='0'.

architecture bhv of Decoder is begin process (en,a) begin if en = '1' then if a="000" then f<="10000000" after 1 ps; elsif a="001" then f<="01000000" after 1 ps; elsif a="010" then f<="00100000" after 1 ps; elsif a="011" then f<="00010000" after 1 ps; elsif a="100" then f<="00001000" after 1 ps; elsif a="101" then f<="00000100" after 1 ps; elsif a="110" then f<="00000010" after 1 ps; else f<="00000001" after 1 ps; end if; else f<="00000000"; end if; end process; end bhv; |

The result can be seen in WF_decoder_2.png The test bench for tha last two waveforms looks like this:

: : en <= '0' after 85 ns, '1' after 115ns, '0' after 135ns, '1' after 145ns; a <= "000" after 0ns, "001" after 10ns, "010" after 20ns, "011" after 30ns, "100" after 40ns, "101" after 50ns, "110" after 60ns, "111" after 70ns, "000" after 80ns, "001" after 90ns, "010" after 100ns, "011" after 110ns, "100" after 120ns, "101" after 130ns, "110" after 140ns, "111" after 150ns; END; |

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Edited by Moderator