Forum: FPGA, VHDL & Verilog 12 Hour Clock problem

von PAUL W. (paulwafflez)

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So I’m on HDLBits trying to work out a problem for a 12 hour clock. I’ve 
tried it two different ways by now. First I’ve tried it with conditional 
statements, and the second way I tried it with case statements. The 
first time, I’m getting and issue that there are some mismatches for my 
Seconds and Minutes outputs and its also saying that the code can not 
simulate. When I do it with the case statements, I'm not getting any 
mismatches, but again it is not simulating.

With the case statement version, its saying that there is an iteration 
limit @ time 0 ps, while for the conditional version, its saying that 
there is an iteration limit @ time 38255 ps. Do I have a loop somewhere 
that I'm not seeing? I will attach both files so you can see the code. 
This is the link to the problem in question 

von Lothar M. (lkmiller) (Moderator)

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PAUL W. wrote:
> Do I have a loop somewhere that I'm not seeing
I don't know Verilog, but this looks alike a combinatorial loop without 
no clock:
   assign #1 h1 = h2;
    assign  #1 m1 = m2;
    assign #1  s1 = s2;
    twelve z1(h1, h2);
    sixty z2(m1, m2);
    sixty z3(s1, s2);
For me the assignment h1=h2 means they are.the same. And so the output 
of the combinatorial function "twelve" is immediately fed back to its 

This here also looks extremely strange:
            h1 <= 4'h2;
            h2 <= 4'h1;
        end else begin   
           if(four & reset)begin 
              h1 <= 4'h2;       // will never ever be reached... 
              h2 <= 4'h1;
           end else if(four & ~reset)

: Edited by Moderator


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