module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    
    reg [3:0] h1, h2, m1, m2, s1, s2;
    reg one, two, three, four, five;
    
    always @ (posedge clk)
        s1 <= reset ? 4'h0 : ( ena ? (reset || s1 == 9 ? 4'h0 : s1 + 1) : s1);
    
    assign one = (s1 == 9) ? 1 : 0;
    
    always @ (posedge clk)
        s2 <= reset ? 4'h0 : ( one ? (reset || s2 == 5 ? 4'h0 : s2 + 1) : s2);
    
    assign two = (s1 == 9) && (s2 == 5) ? 1 : 0;
    
   always @ (posedge clk)
       m1 <= reset ? 4'h0 : ( two ? (reset || m1 == 9 ? 4'h0 : m1 + 1) : m1);
    
    assign three = (m1 == 9) && (s1 == 9) && (s2 == 5) ? 1 : 0;
    
    always @ (posedge clk)
        m2 <= reset ? 4'h0 : ( three ? (reset || m2 == 5 ? 4'h0 : m2 + 1) : m2);
    
    assign four = (m2 == 5) && (m1 == 9) && (s1 == 9) && (s2 == 5) ? 1 : 0;
    
    always @ (posedge clk)begin
        if(reset)begin
            h1 <= 4'h2;
            h2 <= 4'h1;
        end else begin
            if(four & reset)begin
                    h1 <= 4'h2;
            		h2 <= 4'h1;
            end else if(four & ~reset) begin
                    if(h2 == 4'h1 && h1 == 4'h2)begin
                        h2 <= 4'h0;
                        h1 <= 4'h1;
                    end else if(h2 == 4'h1 && h1 != 4'h2)begin
                        h1 <= h1 + 1;
                    end else if(h2 != 4'h1 && h1 != 4'h9)begin
                        h1 <= h1 + 1;
                    end else if(h2 == 4'h0 && h1 == 4'h9)begin
                        h1 <= 4'h0;
                        h2 <= 4'h1;
                    end
            end
        end
    end
        
                    
    assign hh = {h2, h1};
    assign mm = {m2, m1};
    assign ss = {s2, s1};
        assign pm = reset ? 0 : ( hh == 8'h12 && mm == 8'h59 && ss == 8'h59) ? ~pm : pm;
    
endmodule