library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity convertparal_serie is 
port (inA, inB, inC, inD, reloj: in std_logic;
      RD_out: out unsigned (3 downto 0); 
		RD_out2: out unsigned (3 downto 0));					
end convertparalelo_serie;

architecture Behavioral of convertparal_serie is

signal serie: unsigned (3 downto 0);

begin
serie(0)<=inA;
serie(1)<=inB;
serie(2)<=inC;
serie(3)<=inD;

RD_out(0)<=serie(0);
RD_out(1)<=serie(1);
RD_out(2)<=serie(2);
RD_out(3)<=serie(3);

process (reloj)
variable cnt: integer:=0;
begin
   if reloj'event and reloj='1' then
	RD_out2<=serie ROL cnt;
	cnt <= cnt + 1;
end if;
end process;
end Behavioral;