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Forum: FPGA, VHDL & Verilog PSEUDORANDOM NUMBER GENERATOR AND HAMMING CODE DISPLAY ON LED Test Bench


Author: Ed Hower (howerj)
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The  purpose  of  this  project  is  to generate pseudorandom  numbers 
and  display  corresponding hamming code on LED’s present on Spartan3E 
FPGA board. Use X^4 + X + 1 linear feedback shift register  (LFSR)  as 
pseudorandom  generator  circuit.  The  four  D-Flip  Flops  used  in 
LFSR  circuit output 4 -bit output values at 1 Hz in the free running 
mode. The issue I am running into is creating the test bench for the top 
file. Any help would be much appreciated!

Author: Lothar Miller (lkmiller) (Moderator)
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Ed H. wrote:
> top_code.PNG
Please attach your source code as a *.vhd or *.vhdl file. Its extremely 
difficult to edit a heap of pixels...

> The issue I am running into is creating the test bench for the top file.
Show what test bench you have created so far and ask a specific problem 
about that.
A hint: a VHDL test bench is a entity without ports.
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL;  
  
entity tb_top is 
                                   -- empty entity --> testbench
end tb_top; 
  
architecture behavior of tb_top is
   component top
   port( clk : IN  std_logic;
         :
       ); 
   end component; 
    
   signal clk : std_logic := '0';  -- local signals
   :
   :

begin
   uut: top                        -- wire the unit under test
   port map ( clk => clk, 
              :
            ); 
 
   clk <= not clk after 10 ns;     -- generate clock
end;

BTW: why the heck don't your vectors have an element 0? All of them 
range from somthing "downto 1". That's kind of unusual...

: Edited by Moderator
Author: Ed Hower (howerj)
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So something like this?

Author: Lothar Miller (lkmiller) (Moderator)
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Ed H. wrote:
> So something like this?
Yeah something alike...
And what do you get out of design when you run it on this test bench?

One thing:
   uut: top port map ( 
     clk => clk, 
     sw1=> '1',
     sw2=> '1',
     sw3=> '1'
   ); 
Why don't you use your local signals you defined a few lines above that?

Let your port map look this way:
   uut: top port map ( 
     clk => clk, 
     sw1 => sw1,
     sw2 => sw2,
     sw3 => sw3
   );
And ahead of that you can work with initial values:
   signal sw1 : std_logic := '1';
   signal sw2 : std_logic := '1';
   signal sw3 : std_logic := '1';

: Edited by Moderator
Author: Duke Scarring (Guest)
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I prefer the prefix 'tb_' for testbench signals.
So I know everytime if the signal is inside or outside the dut.
   signal tb_sw1 : std_logic := '1';
   signal tb_sw2 : std_logic := '1';
   signal tb_sw3 : std_logic := '1';
...
   uut: top port map ( 
     clk => tb_clk, 
     sw1 => tb_sw1,
     sw2 => tb_sw2,
     sw3 => tb_sw3
   );

Duke

Author: Lothar Miller (lkmiller) (Moderator)
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And of course the output port of the component should be connected to 
a local signal, too...

: Edited by Moderator

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