The purpose of this project is to generate pseudorandom numbers and display corresponding hamming code on LED’s present on Spartan3E FPGA board. Use X^4 + X + 1 linear feedback shift register (LFSR) as pseudorandom generator circuit. The four D-Flip Flops used in LFSR circuit output 4 -bit output values at 1 Hz in the free running mode. The issue I am running into is creating the test bench for the top file. Any help would be much appreciated!
Attached files:
-
top_design.PNG
12 KB -
top_code.PNG
20 KB
Ed H. wrote: > top_code.PNG Please attach your source code as a *.vhd or *.vhdl file. Its extremely difficult to edit a heap of pixels... > The issue I am running into is creating the test bench for the top file. Show what test bench you have created so far and ask a specific problem about that. A hint: a VHDL test bench is a entity without ports.
1 | library IEEE; |
2 | use IEEE.STD_LOGIC_1164.ALL; |
3 | use IEEE.NUMERIC_STD.ALL; |
4 | |
5 | entity tb_top is |
6 | -- empty entity --> testbench
|
7 | end tb_top; |
8 | |
9 | architecture behavior of tb_top is |
10 | component top |
11 | port( clk : IN std_logic; |
12 | :
|
13 | );
|
14 | end component; |
15 | |
16 | signal clk : std_logic := '0'; -- local signals |
17 | :
|
18 | :
|
19 | |
20 | begin
|
21 | uut: top -- wire the unit under test |
22 | port map ( clk => clk, |
23 | :
|
24 | );
|
25 | |
26 | clk <= not clk after 10 ns; -- generate clock |
27 | end; |
BTW: why the heck don't your vectors have an element 0? All of them range from somthing "downto 1". That's kind of unusual...
:
Edited by Moderator
So something like this?
Ed H. wrote: > So something like this? Yeah something alike... And what do you get out of design when you run it on this test bench? One thing:
1 | uut: top port map ( |
2 | clk => clk, |
3 | sw1=> '1', |
4 | sw2=> '1', |
5 | sw3=> '1' |
6 | );
|
Why don't you use your local signals you defined a few lines above that? Let your port map look this way:
1 | uut: top port map ( |
2 | clk => clk, |
3 | sw1 => sw1, |
4 | sw2 => sw2, |
5 | sw3 => sw3 |
6 | );
|
And ahead of that you can work with initial values:
1 | signal sw1 : std_logic := '1'; |
2 | signal sw2 : std_logic := '1'; |
3 | signal sw3 : std_logic := '1'; |
:
Edited by Moderator
I prefer the prefix 'tb_' for testbench signals. So I know everytime if the signal is inside or outside the dut.
1 | signal tb_sw1 : std_logic := '1'; |
2 | signal tb_sw2 : std_logic := '1'; |
3 | signal tb_sw3 : std_logic := '1'; |
4 | ...
|
5 | uut: top port map ( |
6 | clk => tb_clk, |
7 | sw1 => tb_sw1, |
8 | sw2 => tb_sw2, |
9 | sw3 => tb_sw3 |
10 | );
|
Duke
And of course the output port of the component should be connected to a local signal, too...
:
Edited by Moderator
Watch this topic
Disable multi-page viewPlease log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.