library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity tb_top is -- empty entity --> testbench end tb_top; architecture behavior of tb_top is component top port(clk: in std_logic; sw1,sw2,sw3 :in std_logic; h: out std_logic_vector(7 downto 1) ); end component; signal clk : std_logic := '0'; -- local signals signal sw1 : std_logic ; signal sw2 : std_logic ; signal sw3 : std_logic ; begin uut: top port map ( clk => clk, sw1=> '1', sw2=> '1', sw3=> '1' ); clk <= not clk after 10 ns; -- generate clock end;