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Forum: FPGA, VHDL & Verilog Asynchronous 4 Bit Up Counter using D-Flipflops


Author: anjej (Guest)
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Hey,

i am kinda stuck since 2 hours, i can't find anything related in the 
web. so i decided to ask you guys. may be i can get some hints for my 
problem.

first of all. i want to implement a 4 Bit Up Counter using only D 
Flipflop with an asynchronous reset. my problem is i dont know hot to 
"initilize" the flip flops since i get "not initialized" when i use iSim 
in VHDL.

i am only allowed to use AND/NAND gates and the D Flipflop should work 
with a falling edge.


D Flipflop: https://imgur.com/maADKt2

Asynchronous 4-Bit UP Counter: https://imgur.com/g83g5SF

i am very grateful for any help, i am stuck with my ideas right now.

PS: The D Flipflop has to work with only the CLK, D, Q and nQ. The reset 
is for the 4 BIT Counter!

Author: Lothar Miller (lkmiller) (Moderator)
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anjej wrote:
> i am only allowed to use AND/NAND gates and the D Flipflop should work
> with a falling edge.
Simply attach your VHDL file(s) here without invoking screenshots on 
more or less dubious file-sharing portals. Then it's easy to show you 
the solution...

> PS: The D Flipflop has to work with only the CLK, D, Q and nQ. The reset
> is for the 4 BIT Counter!
I thought you must implement that counter using those flipflops...
However:  when it's an asynchronous reset, then it must go to flipflops. 
If it's a synchronous reset then it can go to the combinatorial network 
between the flipflops.

> my problem is i dont know hot to "initilize" the flip flops since i get
> "not initialized" when i use iSim in VHDL.
Try that in the entity's port declaration
q : out := '0';
qn : out := '1';

: Edited by Moderator
Author: anjej (Guest)
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Thank your for your reply.

Lothar M. wrote:
> anjej wrote:
>> i am only allowed to use AND/NAND gates and the D Flipflop should work
>> with a falling edge.
> Simply attach your VHDL file(s) here without invoking screenshots on
> more or less dubious file-sharing portals. Then it's easy to show you
> the solution...

Okay, done.

>> PS: The D Flipflop has to work with only the CLK, D, Q and nQ. The reset
>> is for the 4 BIT Counter!
> I thought you must implement that counter using those flipflops...
> However:  when it's an asynchronous reset, then it must go to flipflops.
> If it's a synchronous reset then it can go to the combinatorial network
> between the flipflops.

Yeah that counter has to be build with those flipflops.
So basically i use my reset input and wire it to all clk's of the 
flipflops?

>> my problem is i dont know hot to "initilize" the flip flops since i get
>> "not initialized" when i use iSim in VHDL.
> Try that in the entity's port declaration
> q : out := '0';
> qn : out := '1';

Thank you i did that, but i did that with the 'd' too. So i got some 
results right now. I am looking if the results are right.

Author: anjej (Guest)
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I corrected a mistake where the out CLR was not correct showing since i 
used the wrong gates. it seems that it works now correctly.

thank your for the advise!

i dont know if it can be shown, i attached the wave file.

Author: Lothar Miller (lkmiller) (Moderator)
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anjej wrote:
> i dont know if it can be shown, i attached the wave file.
Not on my mobile...
A screenshot would be the better choice here. 😉

: Edited by Moderator
Author: -gb- (Guest)
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Take a look at the 74HC193 from the old days:

https://assets.nexperia.com/documents/data-sheet/7...

Page three shows the circuit.

I implemented this circuit in the attached description.

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