Asynchronous 4 Bit Up Counter using D-Flipflops

Thank your for your reply.

Lothar M. wrote:
> anjej wrote:
>> i am only allowed to use AND/NAND gates and the D Flipflop should work
>> with a falling edge.
> Simply attach your VHDL file(s) here without invoking screenshots on
> more or less dubious file-sharing portals. Then it's easy to show you
> the solution...

Okay, done.

>> PS: The D Flipflop has to work with only the CLK, D, Q and nQ. The reset
>> is for the 4 BIT Counter!
> I thought you must implement that counter using those flipflops...
> However:  when it's an asynchronous reset, then it must go to flipflops.
> If it's a synchronous reset then it can go to the combinatorial network
> between the flipflops.

Yeah that counter has to be build with those flipflops.
So basically i use my reset input and wire it to all clk's of the 
flipflops?

>> my problem is i dont know hot to "initilize" the flip flops since i get
>> "not initialized" when i use iSim in VHDL.
> Try that in the entity's port declaration
> q : out := '0';
> qn : out := '1';

Thank you i did that, but i did that with the 'd' too. So i got some 
results right now. I am looking if the results are right.

I corrected a mistake where the out CLR was not correct showing since i 
used the wrong gates. it seems that it works now correctly.

thank your for the advise!

i dont know if it can be shown, i attached the wave file.

Take a look at the 74HC193 from the old days:

https://assets.nexperia.com/documents/data-sheet/74HC_HCT193.pdf

Page three shows the circuit.

I implemented this circuit in the attached description.