---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 13:33:03 11/20/2017 -- Design Name: -- Module Name: Simbox_D_FlipFlop - TEST_D_FlipFlop -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Simbox_D_FlipFlop is end Simbox_D_FlipFlop; architecture TEST_D_FlipFlop of Simbox_D_FlipFlop is component D_Flipflop is port( clk, d : in STD_LOGIC; Q, nQ : out STD_LOGIC ); end component; signal clk_test, d_test : STD_LOGIC := '0'; signal Q_test, nQ_test : STD_LOGIC := '0'; for my_D_Flipflop : D_Flipflop use entity work.D_Flipflop(D_Flipflop_behaviour); begin my_D_Flipflop : D_Flipflop port map( clk => clk_test, d => d_test, Q => Q_test, nQ => nQ_test ); clk_test <= not clk_test after 2ns; d_test <= not d_test after 5ns; end TEST_D_FlipFlop;