-- tb.vhd library IEEE; use IEEE.std_logic_1164.ALL; ENTITY tb is END tb; ARCHITECTURE abc OF tb IS ---------------------------------------------------- --- The parent design, myadder8_top, is instantiated --- in this testbench. Note the component --- declaration and the instantiation. ---------------------------------------------------- COMPONENT PISO is port( brc : in STD_LOGIC; reset : in STD_LOGIC; data: out STD_LOGIC; serial_din1:OUT STD_LOGIC; temp_clk:OUT STD_LOGIC ); end COMPONENT; signal brc : STD_LOGIC; signal reset : STD_LOGIC; signal data: STD_LOGIC; signal serial_din1: STD_LOGIC; signal temp_clk: STD_LOGIC; BEGIN uut: PISO PORT MAP (brc,reset,data,serial_din1,temp_clk); PROCESS BEGIN brc<='1'; wait for 10 ns; brc<='0'; wait for 10 ns; end process; -- stimulus PROCESS BEGIN reset<='1'; wait for 10 ns; reset<='0'; wait for 10 ms; end process; -- stimulus END abc;