library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_textio.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_signed.all; use ieee.numeric_std.all; use ieee.numeric_bit.all; use IEEE.std_logic_arith.all; use IEEE.MATH_REAL.ALL; use IEEE.MATH_complex.ALL; entity comp is port ( clk : in std_logic ); end comp; architecture arch of comp is signal p1: real :=11.0 ; signal n: real :=5797.0 ; signal w: real ; signal word: real :=1024.0; signal sqrt1: real :=0.0; signal g1: real :=0.0; signal k1: real :=0.0 ; begin read: process(clk) begin if clk'event and clk='1' then w<=(word**2.0) mod n ; sqrt1<=w mod p1; if sqrt(sqrt1) mod 1.0/= 0.0 then while sqrt(sqrt1+k1*p1) mod 1.0 /= 0.0 loop k1<=k1+1.0; exit when sqrt(sqrt1+k1*p1) mod 1.0 < 1.0; end loop; g1<=sqrt(sqrt1+k1*p1) mod p1; else g1<=sqrt(sqrt1)mod p1; end if; end if; end process; end arch;