module BCD_adder_dataflow(
	input  [7:0] x, y,
	input        c_in,
	output [7:0] sum,
	output       c_out,
	inout  [7:0] s_tmp, correction,
	inout  	     ac_tmp, ac_correct, ac,
                     c_tmp,  c_correct);
					 
	full_adder fa1 (.x(x[3:0]), .y(y[3:0]), .ci(c_in), .co(ac_tmp));
	full_adder fa2 (.x(correction[3:0]), .y(s_tmp[3:0]), .ci(c_in), .co(ac_correct));
	full_adder fa3 (.x(x[7:4]), .y(y[7:4]), .ci(ac), .co(c_tmp));
	full_adder fa4 (.x(correction[7:4]), .y(s_tmp[7:4]), .ci(c_in), .co(c_correct));
	
	assign s_tmp[3:0] = x[3:0] + y[3:0];
	assign correction[3:0] = (ac_tmp || (s_tmp[3:0] > 9 ? 1 : 0) ) ? 6 : 0;
	assign sum[3:0] = s_tmp[3:0] + correction[3:0];

	assign ac = ac_tmp + ac_correct;
	
	
	assign s_tmp[7:4] = x[7:4] + y[7:4]; 
	assign correction[7:4] = (c_tmp || (s_tmp[7:4] > 9 ? 1 : 0) ) ? 6 : 0;
	assign sum[7:4] = s_tmp[7:4] + correction[7:4];
	
	assign c_out = c_tmp + c_correct;
	
endmodule




module full_adder(
    input x ,y, ci,
	 output s, co);
	 wire s1, c1, c2;
	 
	 half_adder ha_1(x, y,s1, c1);
	 half_adder ha_2(ci, s1,s, c2);
	 or             (co, c1, c2);	 

endmodule




module half_adder(
    input x, y,
	 output s, c);
	 
	 xor (s, x, y);
	 and (c, x, y);	 

endmodule