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help writing testbench for uart
von mike (Guest)

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hi! i am kind a new in the business i have problem to write a testbench 
to the next uart code. any help will be appreciated
(this uart code was found in the web)
1
library ieee;

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    use ieee.std_logic_1164.all;

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    use ieee.std_logic_unsigned.all;

4
5
entity uart is

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    port (

7
        reset       :in  std_logic;

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        txclk       :in  std_logic;

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        ld_tx_data  :in  std_logic;

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        tx_data     :in  std_logic_vector (7 downto 0);

11
        tx_enable   :in  std_logic;

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        tx_out      :out std_logic;

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        tx_empty    :out std_logic;

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        rxclk       :in  std_logic;

15
        uld_rx_data :in  std_logic;

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        rx_data     :out std_logic_vector (7 downto 0);

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        rx_enable   :in  std_logic;

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        rx_in       :in  std_logic;

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        rx_empty    :out std_logic

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    );

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end entity;

22
architecture rtl of uart is

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    -- Internal Variables

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    signal tx_reg         :std_logic_vector (7 downto 0);

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    signal tx_over_run    :std_logic; -- counter that check that we transmit all the data bits.

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    signal tx_cnt         :std_logic_vector (3 downto 0);--the counter that check that we transmit all the data bits.

27
    signal rx_reg         :std_logic_vector (7 downto 0);

28
    signal rx_sample_cnt  :std_logic_vector (3 downto 0);-- the counter that check that we run half of the bit transmit.

29
    signal rx_cnt         :std_logic_vector (3 downto 0);-- the counter that check that we recive all the data bits.

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    signal rx_frame_err   :std_logic;

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    signal rx_over_run    :std_logic;--the flag that check that we recive all the data bits.

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    signal rx_d1          :std_logic;

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    signal rx_d2          :std_logic;

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    signal rx_busy        :std_logic;

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    signal rx_is_empty    :std_logic;

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    signal tx_is_empty    :std_logic;

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begin

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    -- UART RX Logic

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    process (rxclk, reset) begin

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        if (reset = '1') then

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            rx_reg        <= (others=>'0');

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            rx_data       <= (others=>'0');

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            rx_sample_cnt <= (others=>'0');

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            rx_cnt        <= (others=>'0');

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            rx_frame_err  <= '0';

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            rx_over_run   <= '0';

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            rx_is_empty   <= '1';

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            rx_d1         <= '1';

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            rx_d2         <= '1';

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            rx_busy       <= '0';

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        elsif (rising_edge(rxclk)) then

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            -- Synchronize the asynch signal

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            rx_d1 <= rx_in;

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            rx_d2 <= rx_d1;

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            -- Uload the rx data

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            if (uld_rx_data = '1') then

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                rx_data  <= rx_reg;

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                rx_is_empty <= '1';

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            end if;

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            -- Receive data only when rx is enabled

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            if (rx_enable = '1') then

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                -- Check if just received start of frame

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                if (rx_busy = '0' and rx_d2 = '0') then

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                    rx_busy       <= '1';

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                    rx_sample_cnt <= X"1";

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                    rx_cnt        <= X"0";

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                end if;

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                -- Start of frame detected, Proceed with rest of data

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                if (rx_busy = '1') then

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                    rx_sample_cnt <= rx_sample_cnt + 1;

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                    -- Logic to sample at middle of data

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                    if (rx_sample_cnt = 7) then

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                        if ((rx_d2 = '1') and (rx_cnt = 0)) then

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                            rx_busy <= '0';

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                        else

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                            rx_cnt <= rx_cnt + 1;

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                            -- Start storing the rx data

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                            if (rx_cnt > 0 and rx_cnt < 9) then

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                                rx_reg(conv_integer(rx_cnt) - 1) <= rx_d2;

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                            end if;

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                            if (rx_cnt = 9) then

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                                rx_busy <= '0';

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                                -- Check if End of frame received correctly

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                                if (rx_d2 = '0') then

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                                    rx_frame_err <= '1';

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                                else

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                                    rx_is_empty  <= '0';

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                                    rx_frame_err <= '0';

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                                    -- Check if last rx data was not unloaded,

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                                    if (rx_is_empty = '1') then

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                                        rx_over_run  <= '0';

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                                    else

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                                        rx_over_run  <= '1';

94
                                    end if;

95
                                end if;

96
                            end if;

97
                        end if;

98
                    end if;

99
                end if;

100
            end if;

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            if (rx_enable = '0') then

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                rx_busy <= '0';

103
            end if;

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        end if;

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    end process;

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    rx_empty <= rx_is_empty;

107
    

108
    -- UART TX Logic

109
    process (txclk, reset) begin

110
        if (reset = '1') then

111
            tx_reg        <= (others=>'0');

112
            tx_is_empty   <= '1';

113
            tx_over_run   <= '0';

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            tx_out        <= '1';

115
            tx_cnt        <= (others=>'0');

116
        elsif (rising_edge(txclk)) then

117
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            if (ld_tx_data = '1') then

119
                if (tx_is_empty = '0') then

120
                    tx_over_run <= '0';

121
                else

122
                    tx_reg   <= tx_data;

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                    tx_is_empty <= '0';

124
                end if;

125
            end if;

126
            if (tx_enable = '1' and tx_is_empty = '0') then

127
                tx_cnt <= tx_cnt + 1;

128
                if (tx_cnt = 0) then

129
                    tx_out <= '0';

130
                end if;

131
                if (tx_cnt > 0 and tx_cnt < 9) then

132
                    tx_out <= tx_reg(conv_integer(tx_cnt) -1);

133
                end if;

134
                if (tx_cnt = 9) then

135
                    tx_out <= '1';

136
                    tx_cnt <= X"0";

137
                    tx_is_empty <= '1';

138
                end if;

139
            end if;

140
            if (tx_enable = '0') then

141
                tx_cnt <= X"0";

142
            end if;

143
        end if;

144
    end process;

145
    tx_empty <= tx_is_empty;

146
147
end architecture;


  


  



  

  
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    Re: help writing testbench for uart
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Your only work up to now was to copy some piece of VHDL code from 
somewhere from the internet, and now you want somebody else writing a 
test bench for it. Did I figure out that correctly?

I suggest, that YOU start writing this test bench and if there's a 
specific problem you can ask a question.

BTW: wrap the tags [ vhdl ] and [ /vhdl ] without the spaces around your 
VHDL code and you will see a little kind of magic...

BTW2: the code above is not a good one. Its a lousy style to use a 
std_logic_vector for calculating and counting...

  


  



  

  
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    Re: help writing testbench for uart
  


  

    

      von
      
        Hector I.
        (hector_i)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Respected Sir,
I am doing UART as my project.

please elaborate more on your tips.

BTW: wrap the tags [ vhdl ] and [ /vhdl ] without the spaces around your
VHDL code and you will see a little kind of magic...

(where to write this..)

BTW2: the code above is not a good one. Its a lousy style to use a
std_logic_vector for calculating and counting...

(sir, please tell me if this will be lousy , what will be the nice 
idea.?)

  


  




  

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    Re: help writing testbench for uart
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Hector I. wrote:
> BTW: wrap the tags [ vhdl ] and [ /vhdl ] without the spaces around your
> VHDL code and you will see a little kind of magic...
> (where to write this..)
Do it this way:
1
[vhdl]

2
  -- your vhdl code

3
[/vhdl]

And you will get this neatly formated view:
1
  -- your vhdl code


> BTW2: the code above is not a good one. Its a lousy style to use a
> std_logic_vector for calculating and counting...
>
> (sir, please tell me if this will be lousy , what will be the nice
> idea.?)
Use the numeric_std package and the signed/unsigned vectors for 
calculations. Or use an integer for calculations. But don't use 
std_logic_vector for calculations.

For a good working UART look there (its German, try Google translator):
http://www.lothar-miller.de/s9y/categories/42-RS232

  


  




  

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    Re: help writing testbench for uart
  


  

    

      von
      
        FPGA advisor (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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The most appreciated way to get a testbench for P2P-systems like UARt, 
I2C, SPI and such is to join two complementary modules interfacing each 
other vice versa.

Just place your UART against itself and write a CODE to be transmitted 
into it. See if it transmits, if the counter part receives correctly and 
be ready and have done.

  


  




  

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    Re: help VHdl code for radar system integration
  


  

    

      von
      
        Megha (Guest)
      
      


      
    


    

      
    

    

    

      

      

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can u please help us for coding of controlling and monitoring for radar 
design

  


  




  

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    Re: help writing testbench for uart
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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Megha wrote:
> can u please help us for coding of controlling and monitoring for radar
> design
Please start a NEW thread for a NEW question!

And then for getting help YOU must start with something. And then you 
can ask a particular question.

And then add specific information about your target system (ASIC, FPGA, 
µC, ...). And add information about the toolchain (what HDL, or 
programing language).

And then read your whole post as if you do not know anything about your 
task. Because thats how we look at it. If the posted information is 
insufficient: add it.

BTW: don't post DOXC files. Post PDF files or PNG screenshots instead.

  


  




  

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