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VHDL Code works, need help with testbench and isim
von Tai T. (john9686)

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Hi!

I'm working on this function. I need some help. Here is my code. It 
works sythesizes and implements the design. When I create a testbench 
using xilink I get the code attached. I add binary value "222" to 
switches in testbench. When I run isim I get the attached image. Whats 
wrong???


T = Min[Max(A,512),B]xC

CODE:
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library IEEE;

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use IEEE.std_logic_1164.all;

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use IEEE.numeric_std.all;

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entity functionT is

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    port(

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        clk: in std_logic;

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        switches: in std_logic_vector(9 downto 0);

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        output: out std_logic_vector(9 downto 0)

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    );

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end functionT;

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architecture ARCH of functionT is

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--signals

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signal A: unsigned(9 downto 0):=("0110101001"); -- A=425

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signal B: unsigned(9 downto 0);

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signal sig512: unsigned(9 downto 0):=("1000000000"); --sign512=512

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signal T: unsigned(9 downto 0);

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signal x, y, z: unsigned(9 downto 0);

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begin

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    B <= unsigned(switches); --something like that

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    x <= A when A>sig512 else sig512;

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    y <= x when x<B else B;

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    z <= y * 3;

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    T <= z(7 downto 0) & "00";

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    output <= std_logic_vector(T);

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end ARCH;


  


  



  

  
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    Re: VHDL Code works, need help with testbench and isim
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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> testbench_code.txt
None of my VHDL files end up with ".txt"
Why does yours?

> signal A: unsigned(9 downto 0):=("0110101001"); -- A=425
Because signal A is not in a register, it cannot store the assigned 
default value. So one timestep after the first initialisation the signal 
A will become "UUUUUU...". This results in the reported metavalue. Try 
it this way:
> constant A: unsigned(9 downto 0):=("0110101001"); -- A=425

  


  




  

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    Re: VHDL Code works, need help with testbench and isim
  


  

    

      von
      
        Tai T.
        (john9686)
        
      
      


      
    


    

      
    

    

    

      

      

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just copy pasted the testbench.vhd to notepad. here is orginal 
testbench.vhd.

constant A: unsigned(9 downto 0):=("0110101001"); -- A=425
does not work. Is the error coming from my testbench code?
In the image attached the clock is default 0

  


  




  

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    Re: VHDL Code works, need help with testbench and isim
  


  

    

      von
      
        Duke Scarring (Guest)
      
      


      
    


    

      
    

    

    

      

      

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Tai Tai wrote:
> does not work.
You provocate a type mismatch (std_logic_vector vs. unsigned).

With these changes it will work:
1
33c33

2
< --USE ieee.numeric_std.ALL;

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---

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> USE ieee.numeric_std.ALL;

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53c53

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<    signal switches : std_logic_vector(9 downto 0) :=("0011011110"); --A=222;

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---

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>    signal switches : unsigned(9 downto 0) := to_unsigned( 222, 10);

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66c66

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<           switches => switches,

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---

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>           switches => std_logic_vector( switches),


Duke

  


  




  

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