Help with Vhdl and verilog

Hi Marho

> Marho Efeduma wrote:
> i got the truth table i know how to know the SOP and produce it in forms
> of gates. But my lecturer wants us to create a vhdl and verilog code for
> the problem. Am new to verilog and am finding it difficult. Please i
> need help with the codes

I'm here to the rescue!

I can undertake your project for a minimal sum. Let me know if you are 
interested in order to discuss this further.

Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

Nikolaos Kavvadias wrote:
> Hi Marho

> I'm here to the rescue!
>
> I can undertake your project for a minimal sum. Let me know if you are
> interested in order to discuss this further.
>
> Best regards
> Nikolaos Kavvadias
> http://www.nkavvadias.com

Nikolaos Thanks a lot. I am very interested and would love your help. 
How do i get across to you?

Hi Marho,

please contact me via email.

You can find my email at the www.nkavvadias.com homepage

where it says "Pricing details and arrangements..."


Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

HI nikolaos,
 i sent you a mail already i am waiting for your response.

Cheers
Marho Efeduma

Hey Valko,

do you waste your life solving computational tasks for free?

Geez.

Still this doesn't make justice.

Dear Marho, my job is done here.

Have a nice Modelsim (or GHDL) session!

Yeah, you too... Are you into this field? Which country do you live in? 
Can you share any samples (even screenshots) from your portfolio?

OFFTOPIC: I'm looking to hire someone for LLVM backend development. It 
will be a short 90-day task. Me and my cofounder can pay a reasonable 
sum, close to what you would get on Google Summer of Code (without the 
mentoring of course).

In case you are interested to discuss further on technical stuff. It 
will be a rainy weekend here so plans are basically to continue 
development. Fri-Thu will be sunny and best option for outdoor 
activities.

I mean Mon-Thu will be sunny :) Sorry for the OT post, still interested 
in discussing technical on VHDL for instance.

Hi Valko,

Thanks a lot, i have ran the vhd code on my modelsim and it compiled and 
is outputing waveforms. One last thing..i am feeling really backwards at 
the moment because i just got introduced to modelsim verilog and vdl 
coding. I know it sounds really selfish of me but please is there anyway 
you could help me with the verilog code for same project. CHeers

Hi Valko,

I think you should write the Verilog code for Marho.

Marho, if you want to roll your own, check out the vhd2vl free tool. It 
is capable of handling a certain VHDL subset, however you will have to 
make a second pass fixing any syntactical mistranslations.

Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com

Motte wrote:
> You might be able to help yourself:
> http://www.syncad.com/verilog_vhdl_translator.htm
>
> Google can suggest other tools which can translate VHDL to Verilog.
> Since the code is not that difficult it shouldn't cause any troubles
> when you're using translating tools.
>
> Good luck!

 I used the verilog_vhdl_translator to translate the Vdhl file to 
verilog. I tried compiling and i dont get any wave output on my 
modelsim. Not really to sure about the code maybe its not properly 
translated because when i compile it, it doesn't show any errors

Hi Marho

>  I used the verilog_vhdl_translator to translate the Vdhl file to
> verilog. I tried compiling and i dont get any wave output on my
> modelsim. Not really to sure about the code maybe its not properly
> translated because when i compile it, it doesn't show any errors

You had to take my offer. Now you are spending the 2nd day in a row to 
resolve this simple task. I don't think you properly balance work for 
life.

Anyway, since I'm not getting not a single dime out of this, check out 
your testbench. Something is missing. Do you understand what is missing 
from there?

Nikolaos Kavvadias wrote:
> Hi Marho
>
>>  I used the verilog_vhdl_translator to translate the Vdhl file to
>> verilog. I tried compiling and i dont get any wave output on my
>> modelsim. Not really to sure about the code maybe its not properly
>> translated because when i compile it, it doesn't show any errors
>
> You had to take my offer. Now you are spending the 2nd day in a row to
> resolve this simple task. I don't think you properly balance work for
> life.
>
> Anyway, since I'm not getting not a single dime out of this, check out
> your testbench. Something is missing. Do you understand what is missing
> from there?

no i dont...please just help me out..cheers

Hi Marho

collaborative culture is against Greek custom.

In Greece, everyone is on his own, unless he/she pays for "official" 
help. This is how things are since forever.

Best regards
Nikolaos Kavvadias

Nikolaos Kavvadias wrote:
> Hi Marho
>
> collaborative culture is against Greek custom.
>
> In Greece, everyone is on his own, unless he/she pays for "official"
> help. This is how things are since forever.
>
> Best regards
> Nikolaos Kavvadias

oh well...hv fun then...cant really seem to persuade you to help even it 
the most minimal way.