------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ------------------------------------------------------------------------------- ENTITY parking_lot_tb IS END ENTITY parking_lot_tb; ------------------------------------------------------------------------------- ARCHITECTURE tb OF parking_lot_tb IS COMPONENT parking_lot IS PORT ( p1 : IN STD_LOGIC; p2 : IN STD_LOGIC; p3 : IN STD_LOGIC; p4 : IN STD_LOGIC; a1 : OUT STD_LOGIC; a2 : OUT STD_LOGIC; a3 : OUT STD_LOGIC; a4 : OUT STD_LOGIC); END COMPONENT parking_lot; -- component ports SIGNAL p1 : STD_LOGIC := '0'; SIGNAL p2 : STD_LOGIC := '0'; SIGNAL p3 : STD_LOGIC := '0'; SIGNAL p4 : STD_LOGIC := '0'; SIGNAL a1 : STD_LOGIC; SIGNAL a2 : STD_LOGIC; SIGNAL a3 : STD_LOGIC; SIGNAL a4 : STD_LOGIC; -- clock signal Clk : std_logic := '1'; BEGIN -- ARCHITECTURE tb -- component instantiation DUT: parking_lot PORT MAP ( p1 => p1, p2 => p2, p3 => p3, p4 => p4, a1 => a1, a2 => a2, a3 => a3, a4 => a4); p1 <= NOT p1 AFTER 100 ns; p2 <= NOT p2 AFTER 200 ns; p3 <= NOT p3 AFTER 400 ns; p4 <= NOT p4 AFTER 800 ns; END ARCHITECTURE tb; ------------------------------------------------------------------------------- CONFIGURATION parking_lot_tb_tb_cfg OF parking_lot_tb IS FOR tb END FOR; END parking_lot_tb_tb_cfg; -------------------------------------------------------------------------------