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Forum: FPGA, VHDL & Verilog timing constraint


timing constraint
von ISE xilinks (Guest)

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""ERROR:HDLParsers:3305 - 
"C:/Users/PROXIMEDIA/Documents/ISE-file/scrambler/scrambler.vhd" Line 
301.  The actual value (Signal 'widthWCDMA') associated with a generic 
must be a globally static expression.""

How shall we do it?

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Re: timing constraint
von Lothar M. (Company: Titel) (lkmiller) (Moderator)

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ISE xilinks wrote:
> How shall we do it?
You already DID it.
The actual question must be: how can we avoid it?

And then it would be VERY helpful to see the code that results in the 
posted problem. Or how the heck should anyone find out what the problem 
may be?

But usually this error results from dynamic borders or ranges that 
should or must be static when synthesizing the design...

BTW: by reading the word "scrambler" i become kind of suspicious:
http://embdev.net/search?query=scrambler

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Re: timing constraint
von Dajana K. (hummer90)

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okay, without any code it is definitely a bit difficult to solve the 
problem.

But the compiler has a problem with your definition in your entity.

You declared some "constant" value in your generic section in your 
entity and the compiler wants a constant in the architecture I think.

Maybe it could fix your problem.

Regards

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