hi... i was having some problem in running a while loop..even though i have given condition still it goes infinite..help me out..Thanx in advance. library ieee,work; USE ieee.std_logic_1164.all; USE work.myfunc.find; USE work.myfunc1.diffarray; USE work.myfunc2.subarray1; ENTITY division IS port(divi,divs : in bit_vector(7 downto 0); quot,rema :out bit_vector(7 downto 0)); END ENTITY; Architecture div of division is signal cdivi,cdivs,msubarray,crema: bit_vector(7 downto 0); signal hpdivi,hpdivs,maindiff,test1,i,tcount: integer := 0; begin process(divi,divs,cdivi,cdivs,maindiff,hpdivs,test1,msubarray,crema) variable vsubarray,vdivs,vcrema : bit_vector(7 downto 0); variable vhpdivi,vhpdivs,vhpdivs1,vdiff,test,count :integer :=0; begin vcrema := divi; cdivs <= divs; vdivs := cdivs; while(vcrema > vdivs) loop count := count + 1; cdivi <= vcrema; find(cdivi,vhpdivi); find(cdivs,vhpdivs); maindiff <= vhpdivi - vhpdivs ; vdiff := maindiff; hpdivs <= vhpdivs ; test := hpdivs + maindiff ; test1 <= test; -- formation of subtractor array for i in 0 to hpdivs loop vsubarray(test - i) := vdivs(hpdivs - i); end loop; msubarray <= vsubarray; diffarray(cdivi,msubarray,crema); vcrema := crema ; exit when count > 4; --formation of quotient end loop; tcount <= count; rema <= crema; end process; end div;
Can you deliver a testbench to your code?
hi..thanx for the reply..actually i am in IT branch.. so i dont have much knowledge in VHDL..just know the basic syntax..i dont know wat test bench is..basically i m implementing an algorithm for division using the concept of vedic maths..m sorry..
Hi akshay bhandari, you cant Do what you want it that matter, Loop isnt a construct to control iterations like you do in software. Loop meens your building paralel hardware.
I think a "hanging" loop can happen in simulation, but I think a synthesis tool would present some errors ;-) OR it won't function as expected. Remember: don't use LOOP in VHDL if you are a beginner and you want to synthesize your design If you use it, use it carefully and double-check that your synthesis tool likes LOOP and handles it the way you planned it. It would be better to think about the hardware logic that does your job and implement it the right way then (maybe there will be LOOP in it).
akshay bhandari wrote: > hi..thanx for the reply..actually i am in IT branch.. so i dont have > much knowledge in VHDL..just know the basic syntax.. This way you might be able to write VHDL that runs in the simulator, but never something that can be synthesized. Learn the basics of synchronous processes in VHDL, and follow these rules: http://embdev.net/articles/VHDL