VHDL_loop problem

hi...
i was having some problem in running a while loop..even though i have 
given condition still it goes infinite..help me out..Thanx in advance.


library ieee,work;
USE ieee.std_logic_1164.all;
USE work.myfunc.find;
USE work.myfunc1.diffarray;
USE work.myfunc2.subarray1;

ENTITY division IS
port(divi,divs : in bit_vector(7 downto 0);
quot,rema :out bit_vector(7 downto 0));
END ENTITY;


Architecture div of division is

signal cdivi,cdivs,msubarray,crema: bit_vector(7 downto 0);
signal hpdivi,hpdivs,maindiff,test1,i,tcount: integer := 0;

begin

process(divi,divs,cdivi,cdivs,maindiff,hpdivs,test1,msubarray,crema)

variable vsubarray,vdivs,vcrema : bit_vector(7 downto 0);
variable vhpdivi,vhpdivs,vhpdivs1,vdiff,test,count :integer :=0;

begin

vcrema := divi;
cdivs <= divs;
vdivs := cdivs;

while(vcrema > vdivs) loop
count := count + 1;
cdivi <= vcrema;
find(cdivi,vhpdivi);
find(cdivs,vhpdivs);
maindiff <= vhpdivi - vhpdivs ;
vdiff := maindiff;
hpdivs <= vhpdivs ;
test := hpdivs + maindiff ;
test1 <= test;

-- formation of subtractor array
for i in 0 to hpdivs loop
vsubarray(test - i) := vdivs(hpdivs - i);
end loop;
msubarray <= vsubarray;

diffarray(cdivi,msubarray,crema);
vcrema := crema ;

exit when count > 4;
--formation of quotient
end loop;
tcount <= count;
rema <= crema;

end process;
end div;