Search results for "111"

File

bm01.S

151, (unsigned char)143, (unsigned char)135, (unsigned char)127, (unsigned char)119, (unsigned char)111, (unsigned char)103, (unsigned char)96, (unsigned char)88, (unsigned char)80, (unsigned char)73, (unsigned char)66, (unsigned char)59, (unsigned char)52, (unsigned char)46, (unsigned char)40, (unsigned

in „Initialwert von globalen Variablen zur Laufzeit verwenden“ · Mikrocontroller und Digitale Elektronik · 2019-12-11 11:58

File

lcd.c

, 89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115, 90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116, 91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117, 92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118, 93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119, 94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120

in „Programm startet neu bei Zugriff auf array“ · Mikrocontroller und Digitale Elektronik · 2013-02-05 21:07

File

full.vhdl.txt

:= SBOX_LOOKUP(state(127 downto 120)); b(119 downto 112) := SBOX_LOOKUP(state(119 downto 112)); b(111 downto 104) := SBOX_LOOKUP(state(111 downto 104)); b(103 downto 96) := SBOX_LOOKUP(state(103 downto 96)); b(95 downto 88) := SBOX_LOOKUP(state(95 downto 88)); b(87 downto 80) := SBOX_LOOKUP(state(87

in „VHDL coding Question“ · FPGA, VHDL & Verilog · 2014-11-27 06:46

PDF

kurve_ntc.pdf

4 5 6 7 8 9 10 11 12 13 3 35 1680 -10 3790,39 2350 2100 1680 1350 1050 703 580 438 358 267 196 161 111 4 23 1350 -5 2977,5 100 60 35 23 15 8 6 4 3 2 1,3 1 0,6 5 15 1050 0 2356,24 2350 2100 1680 1350 1050 703 580 438 358 267 196 161 111 6 8 703 5 1877,62 1850 1800 1505 1235 975 663 550 418 343 257 189,5

in „NTC Softwarelinearisierung“ · Mikrocontroller und Digitale Elektronik · 2007-07-02 17:24

File

vhdl_code.vhd

Low Pass Filter library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.std_logic_arith.all; entity lab111 is Port ( clk : in STD_LOGIC; din : in STD_LOGIC_VECTOR (15 downto 0); dout : out STD_LOGIC_VECTOR (15 downto 0)); end lab111; architecture rtl of lab111 is type tdelay is array (7 downto 0) of std_logic_vector

in „How to instantiate another vhd file inside testbench, where the testbench is used for opening files“ · FPGA, VHDL & Verilog · 2024-01-06 19:36

File

TX.vhd

9600-- 2600 when "100", -- 19200-- 1300 when "101", -- 38400-- 866 when "110", -- 57600-- 432 when "111", --115200-- --108 when "111", -- 460800 --54 when "111", -- 921600 5200 when others; TX_proc: process(Clk) begin if(Clk'EVENT and Clk = '1') then --txstart <= START; IF (TX_FLG = '0' and START = '1

in „UART interface on FPGA“ · FPGA, VHDL & Verilog · 2015-03-02 19:53

File

error_xc8.txt

%f:%%l: advisory: (%%n) %%s" -obuild/default/production/main_tmp.p1 main_tmp.c cFL.h:77: warning: (111) redefining preprocessor macro "__delay_us" (C:\Program Files (x86)\Microchip\xc8\v1.20\include\pic18.h: 150) cFL.h:78: warning: (111) redefining preprocessor macro "__delay_ms" (C:\Program Files (x86)\Microchip\xc8\v1.20\include\pic18.h: 151) cFL.h:92: warning: (111) redefining preprocessor macro "__EEPROM_DATA" (C:\Program Files (x86)\Microchip\xc8\v1.20\include\pic18.h: 63) (908) exit status = 1 make[2]: *** [build/default/production/main_tmp.p1] Error 1 make

in „Erklärung für Macrodefinition wird benötigt“ · Mikrocontroller und Digitale Elektronik · 2014-03-18 14:48

File

glcd_data.h

SMALL_FONT_6_106, SMALL_FONT_6_107, SMALL_FONT_6_108, SMALL_FONT_6_109, SMALL_FONT_6_110, SMALL_FONT_6_111, SMALL_FONT_6_112, SMALL_FONT_6_113, SMALL_FONT_6_114, SMALL_FONT_6_115, SMALL_FONT_6_116, SMALL_FONT_6_117, SMALL_FONT_6_118, SMALL_FONT_6_119, SMALL_FONT_6_120, SMALL_FONT_6_121, SMALL_FONT_6_122,

in „Merkwürdigkeit mit PROGMEM Array“ · Mikrocontroller und Digitale Elektronik · 2009-11-25 14:31

File

tb_real_test.vhd

architecture Behave of tb_real_test is signal a : real := 23456789.0; begin process (a) variable j : real := 111.1; begin if a=a*j/111.1 then report("equal"); else report("different!"); end process; end;

in „Active-HDL design“ · FPGA, VHDL & Verilog · 2015-12-16 14:37

PDF

SDI94Ah.pdf

compression force: 1433N @SOC100% #20 105 141 189 1326 #21 106 171 201 1044 #22 120 144 162 1980 #23 111 156 153 1674 #24 111 141 183 1056 #25 105 144 153 1683 #26 #27 114 168 177 1740 120 156 180 1074 #28 135 168 195 1875 #29 102 153 162 885 #30 105 162 171 1617 Page 38 Customer | Confidential | 31/12

in „Looking for a good Lithum battery data book with characterization“ · Analog Circuits · 2021-01-31 17:19

File

fivebit.vhd

<= data; --Circular left shift elsif SEL = "110" then data <= data; --1s' complement elsif SEL = "111" then data <= data; --2s' complement (SEL = "111") end if; end if; end process; end Behavioral;

in „VHDL project : 5 bit shift reg“ · FPGA, VHDL & Verilog · 2017-04-23 16:09

File

disp4dig.vhd

according picture shown above -- case digit is when x"0" => d7 <= b"100_0000"; when x"1" => d7 <= b"111_1001"; when x"2" => d7 <= b"010_0100"; when x"3" => d7 <= b"011_0000"; when x"4" => d7 <= b"001_1001"; when x"5" => d7 <= b"001_0010"; when x"6" => d7 <= b"000_0010"; when x"7" => d7 <= b"111_1000";

in „VHDL Seven Segment Decoder“ · FPGA, VHDL & Verilog · 2020-06-14 15:09

File

Motorsteuerung.c

Bitspeicher fuer Taste 3 bool motor2=0; // Bitspeicher fuer Taste 4 bool timertick; // Bit-Botschaft alle 0,111ms (bei Interrupt) bool takt10ms; // Bit-Botschaft alle 10ms bool takt100ms; // Bit-Botschaft alle 100ms void motor(void); void lese_Eingang(void); void timer0(void); void pwm_generator(void); // Hauptprogramm

in „Probleme mit PWM Erzeugung“ · Mikrocontroller und Digitale Elektronik · 2011-01-09 23:39

File

Motorsteuerung.c

Bitspeicher fuer Taste 3 bool motor2=0; // Bitspeicher fuer Taste 4 bool timertick; // Bit-Botschaft alle 0,111ms (bei Interrupt) bool takt10ms; // Bit-Botschaft alle 10ms bool takt100ms; // Bit-Botschaft alle 100ms void motor(void); void lese_Eingang(void); void timer0(void); void pwm_generator(void); // Hauptprogramm

in „Probleme mit PWM Erzeugung“ · Mikrocontroller und Digitale Elektronik · 2011-01-10 16:45

File

arbitraryfunctiongenerator.c

218,215,213,211,208,206,203,201,198,195,193,190,187,184,181,179, 176,173,170,167,164,161,158,155,152,148,145,142,139,136,133,130, 126,123,120,117,114,111,108,104,101,98,95,92,89,86,83,80, 77,75,72,69,66,63,61,58,55,53,50,48,45,43,41,38, 36,34,32,30,28,26,24,22,20,19,17,16,14,13,11,10, 9,8,7,6,5,4,3,3,2,2,1,1,0,0,0,0, 0,0,0,1,1,1,2,2,3,4,4,5,6,7,8,10,

in „Anfängerfehler (?) mit Interrupts“ · Mikrocontroller und Digitale Elektronik · 2012-04-07 17:14

PDF

AD2500_Macro_Assembler_V402_Manual_Appendices.pdf

E 01000101 105 069 45 F 01000110 106 070 46 G 01000111 107 071 47 H 01001000 110 072 48 I 01001001 111 073 49 J 01001010 112 074 4A K 01001011 113 075 4B L 01001100 114 076 4C M 01001101 115 077 40 N 01001110 116 078 4E 0 01001111 117 079 4F P 01010000 120 080 50 0 01010001 121 081 51 R 01010010 122

in „2500 A.D. Z80 Macro Assembler“ · Mikrocontroller und Digitale Elektronik · 2021-02-13 18:13

File

CRC.o.lst

text._ZN6TZApp4CCrc9Crc32FastEmm,"ax",%progbits 109 .align 2 110 .global _ZN6TZApp4CCrc9Crc32FastEmm 111 .thumb 112 .thumb_func 114 _ZN6TZApp4CCrc9Crc32FastEmm: 115 .LFB134: 44:../CRC.cpp **** /** Berechnet die Checksumme für einen einzelnen 32-bit Wert (Hardware-CRC) 45:../CRC.cpp **** * 46:../CRC.cpp

in „Problem mit GCC-Optimierung“ · Mikrocontroller und Digitale Elektronik · 2013-12-02 16:43

PDF

DisAsm-MI6311.pdf

EQU $111F0E EXT_0774 EQU $111F10 EXT_0775 EQU $111F1A EXT_0776 EQU $111F24 EXT_0777 EQU $111F2E EXT_0778 EQU $111F38 EXT_0779 EQU $111F42 EXT_077A EQU $111F4C EXT_077B EQU $111F4D EXT_077C EQU $111F4E EXT_077D EQU $111F50 EXT_077E EQU $111F54 EXT_077F EQU $111F58 EXT_0780 EQU $111F5C EXT_0781 EQU $111F60 EXT_0782 EQU $111F64 EXT_0783 EQU $111F68 EXT_0784 EQU $111F6C EXT_0785 EQU $111F70 EXT_0786 EQU $111F74 EXT_0787

in „Suche Simulator für Motorola 68k“ · Mikrocontroller und Digitale Elektronik · 2019-11-12 15:54

File

main_medium.lst

= 2; \ 000020 A881 MOV R0,SP \ 000022 7602 MOV @R0,#0x2 109 uint8 len = 1; 110 uint16 offset = 0; 111 uint8 method = 0; 112 113 114 value ++; \ 000024 06 INC @R0 115 116 while(1) { 117 WriteAttrCB( 0, (gattAttribute_t*)&att, (uint8*)&value, len, offset, method ); \ ??main_0: \ 000025 ; Setup parameters

in „IAR (8051) immer noch mit Bug“ · Mikrocontroller und Digitale Elektronik · 2016-02-28 00:48

Image

Software-Screenshot einer Terminal-Anwendung mit Datenliste

Counter = 91 Counter = 94 Counter = 97 Counter = 100 Counter = 102 Counter = 105 Counter = 108 Counter = 111 Counter = 115 Clear Add Hexadecimal Values Show Timestamp Automatically Scroll to End DEU 04.01.2025

in „Atmel Studio 7: Terminal Window installieren“ · Mikrocontroller und Digitale Elektronik · 2025-01-04 22:58 · Screenshots

Software-Screenshot einer Terminal-Anwendung mit Datenliste

File

TestPIC18F25k22.c

void main() { /* OSCCON = 80; OSCCON2.MFIOSEL = 0; // 111: 16 MHz OSCCON.IRCF2 = 1; // 110: 8 MHz OSCCON.IRCF1 = 0; // 101: 4 MHz OSCCON.IRCF0 = 0; // 100: 2 MHz <-- aktiv */ TRISB=0; ANSELB=0; LATB =0xFF; while (1) { LATB1_bit =1; Delay_ms(20); LATB1_bit

in „PIC 18F25k22 mit mikroC Pro“ · Mikrocontroller und Digitale Elektronik · 2022-10-23 13:40

File

getval.c

; // wanted count of numbers read } #define COUNT 4 int main( void ) { char* input = "*127,255,001,111#"; uint8_t colors[COUNT]; while (true) { get_vals(input, colors, COUNT); } }

in „String parsen und zahlen Zahlen per "atoi" extrahieren klappt nicht“ · Mikrocontroller und Digitale Elektronik · 2018-12-07 13:46

File

Bin.c51

#y >> 10 & 32 \ | 0##y >> 12 & 64 \ | 0##y >> 14 & 128 ) test() { P0 = B8(1); P0 = B8(11); P0 = B8(111); P0 = B8(0000111); P0 = B8(1000); P0 = B8(10000000); P0 = B8(11111111); }

in „Binär -- wie in C schreiben?“ · Mikrocontroller und Digitale Elektronik · 2006-10-11 15:28

File

PWM.c

TCCR1A = 0; //Set timer to 0; ICR1 = 19999; //Puls wird alle 20ms gesendet; TCCR1A = (1<<WGM11); //WGM 111 == FAST PWM; TCCR1B = (1 << WGM13) | (1<<WGM12) | (1 << CS11); //Prescaler = 8; DDRB |= _BV(5) | _BV(6); //port 5 und 6 als Output; // TCCR1A |= 2 << 6; TCCR1A |= 2 << 4; // OCR1A = ICR1 * 2 /20; OCR1B

in „Fast PWM Funktioniert nicht wirklich“ · Mikrocontroller und Digitale Elektronik · 2012-07-15 18:15

File

Main.c

init_bittiming(); init_transmitter(); init_receiver(); controller_normal_mode(); modify_register(CANCTRL, 0b111,0b101); modify_register(BFPCTRL, 0b00101010, 0b00101000); uint8_t PD2_pressed_flag = 0; while(1==1){ if((PIND & (1<<PD7)) == 0){ modify_register(BFPCTRL, 0b00101010, 0b00001000); Message *message; handle_interrupt

in „Problem durch Optimierung -Os“ · Mikrocontroller und Digitale Elektronik · 2011-05-08 01:55

Image

PuTTY Terminal Ausgabe ESP-IDF Bootvorgang

heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM I (232) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM I (238) heap_init: At 4008CB98 len 00013468 (77 KiB): IRAM I (244) spi_flash: detected chip: generic I (247) spi_flash: flash io: dio I (250) spi_flash: Detected size (4096k) larger than

in „Keine Kommunikation zu esp32 möglich“ · Mikrocontroller und Digitale Elektronik · 2025-08-17 11:47 · Screenshots

File

mux_8x1.vhd

011" => Y <= I(3); when "100" => Y <= I(4); when "101" => Y <= I(5); when "110" => Y <= I(6); when "111" => Y <= I(7); when others => Y <= '0'; end case; end process; end Behavioral;

in „VHDL project : 5 bit shift reg“ · FPGA, VHDL & Verilog · 2017-04-21 11:49

File

main.c

nW: %i",color[3]); #endif // DEBUG return 0; } int main() { printf("start\n"); parse("*127,255,001,111#"); return 0; }

in „String parsen und zahlen Zahlen per "atoi" extrahieren klappt nicht“ · Mikrocontroller und Digitale Elektronik · 2018-12-04 17:29

File

part3_revised.vhd

<= (A + (NOT B)); when "101" => G <= ((NOT B) + A + '1'); when "110" => G <= ((NOT A) + B); when "111" => G <= ((NOT A) + B + '1'); when others => null; end case; end process ARTH; end Behavioural;

in „Design of 4-bit ALU“ · FPGA, VHDL & Verilog · 2011-01-14 02:33

File

five_bit_tb.vhd

clockk_period*8; SEL <= "101"; wait for clockk_period*8; SEL <= "110"; wait for clockk_period*8; SEL <= "111"; wait for clockk_period*8; SEL <= "000"; wait for clockk_period; SEL <= "001"; wait; end process; END;

in „VHDL project : 5 bit shift reg“ · FPGA, VHDL & Verilog · 2017-04-22 23:32

Image

ST MB2230A Erweiterungsplatine

SB94 SB95 SB96 SB97 SB98 SB99 SB100 SB101 SB102 SB103 SB104 SB105 SB106 SB107 SB108 SB109 SB110 SB111 SB112 SB113 SB114 SB115 SB116 SB117 SB118 SB119 SB120 SB121 SB122 SB123 SB124 SB125 SB126 SB127 SB128 SB129 SB130 SB131 SB132 SB133 SB134 SB135 SB136 SB137 SB138 SB139 SB140 SB141 SB142 SB143 SB144

in „LoRA-Cloud vor Abschaltung, STM32-WLAN-Modul, neue Weltraum-Bauteile uvam“ · Mikrocontroller und Digitale Elektronik · 2025-06-27 23:53 · Board photos

File

five_bit_tb.vhd

101"; wait for 60 ns; --Circular left shift SEL <= "110"; wait for 60 ns; --1s' complement SEL <= "111"; wait for 60 ns; --2s' complement SEL <= "000"; wait for 10 ns; --Reset SEL <= "001"; wait; --Parallel loading end process; END;

in „VHDL project : 5 bit shift reg“ · FPGA, VHDL & Verilog · 2017-04-23 16:09

File

part3.vhd

<= (A + (NOT B)); when "101" => G <= ((NOT B) + A + '1'); when "110" => G <= ((NOT A) + B); when "111" => G <= ((NOT A) + B + '1'); when others => null; end case; end process ARTH; end Behavioural;

in „Design of 4-bit ALU“ · FPGA, VHDL & Verilog · 2011-01-14 01:25

File

TB.txt

Tsel <= "100"; wait for 10 ns; Tsel <= "101"; wait for 10 ns; Tsel <= "110"; wait for 10 ns; Tsel <= "111"; wait for 10 ns; end process; end architecture behavioral;

in „to_unsigned()“ · FPGA, VHDL & Verilog · 2013-07-15 12:07

File

Uart8Transmitter.v

DATA_BITS: begin // Send 8 data bits out <= data[bitIdx]; done <= 1'b0; busy <= 1'b1; if (bitIdx == 3'b111) begin bitIdx <= 3'b0; state <= STOP_BIT; end else begin bitIdx <= bitIdx + 1'b1; end end STOP_BIT: begin // Send out Stop bit (high) out <= 1'b1; // Send stop bit state <= DONE; end DONE: begin if

in „Connecting 7 in 1 Soil Sensor with GW1NSR-4C using UART“ · FPGA, VHDL & Verilog · 2024-07-20 12:08

File

i2c.c

) { i2caddr = 2; } // 110 if (i2caddr1 == 1 && i2caddr2 == 1 && i2caddr3 == 0) { i2caddr = 3; } // 111 if (i2caddr1 == 1 && i2caddr2 == 1 && i2caddr3 == 1) { i2caddr = 4; } // 101 if (i2caddr1 == 1 && i2caddr2 == 0 && i2caddr3 == 1) { i2caddr = 5; } // 001 if (i2caddr1 == 0 && i2caddr2 == 0 && i2caddr3

in „EEPROM Adresse über 255 und SOFT PWM Frage/Anliegen“ · Mikrocontroller und Digitale Elektronik · 2020-11-07 13:34

File

fcntl.lst

mode) { 107 .stabn 68,0,53,.LM5-open 108 .LM5: 109 /* prologue: frame size=0 */ 110 0014 9F92 push r9 111 0016 AF92 push r10 112 0018 BF92 push r11 113 001a CF92 push r12 114 001c DF92 push r13 115 001e EF92 push r14 116 0020 FF92 push r15 117 0022 0F93 push r16 118 0024 1F93 push r17 GAS LISTING c:\windows

in „Compiler-Fehler?“ · Mikrocontroller und Digitale Elektronik · 2006-10-11 10:59

File

code.v

byte_sub Port map (cypher1(119 downto 112),gclock,rst,e1,e2,data2); A3 : byte_sub Port map (cypher1(111 downto 104),gclock,rst,e1,e2,data3); A4 : byte_sub Port map (cypher1(103 downto 96),gclock,rst,e1,e2,data4); A5 : byte_sub Port map (cypher1(95 downto 88),gclock,rst,e1,e2,data5); A6 : byte_sub Port

in „VHDL coding Question“ · FPGA, VHDL & Verilog · 2014-11-26 20:00

File

Uart8Receiver.v

b10: begin // DATA_BITS state receivedData[bitIdx] <= in; // Collecting data bits if (bitIdx == 3'b111) begin bitIdx <= 3'b0; out <= receivedData; // Store received byte state <= 2'b11; // Transition to STOP_BIT state end else begin bitIdx <= bitIdx + 3'b1; end end 2'b11: begin // STOP_BIT state if (

in „Connecting 7 in 1 Soil Sensor with GW1NSR-4C using UART“ · FPGA, VHDL & Verilog · 2024-07-20 12:08

PDF

MSP430_Tools.pdf

Data I/O Family EVK FET (IAR Emulator PRG Gessler Systems) (Goepel) (hitex) Microsystem (SMS) MSP430C111 MSP430 not MSP-FET EW430 MSP430 DProbe430- MSP- MSP430C112 x11x(1) available 430X110 Ocean DP110 PRGS430 not not not MSP430C1111 supported supported supported MSP430C1121 MSP430P112 yes yes MSP430F110

in „CD-Inhalt vom MSP430 Development Tool (ez430)“ · Mikrocontroller und Digitale Elektronik · 2024-07-24 10:05

File

testmux.vhd

Tsel <= "100"; wait for 10 ns; Tsel <= "101"; wait for 10 ns; Tsel <= "110"; wait for 10 ns; Tsel <= "111"; wait for 10 ns; end process; end architecture behavioral;

in „to_unsigned()“ · FPGA, VHDL & Verilog · 2013-07-15 12:53

File

spim.v

reg [2:0]curr; reg shifting; reg loading; reg done; reg w1,w2; reg [7:0]sreg; wire s8b=(bin2gray(3'b111)==bitctr); wire firstbit=(bin2gray(3'b000)==bitctr); wire [2:0]bitctr; always @(posedge clk or posedge rst) if(rst) begin s1<=`S_IDLE; curr<=`CMD_NONE; end else case(s1) `S_IDLE: if(done && req) begin

in „Verilog Simple SPI Code?“ · FPGA, VHDL & Verilog · 2017-09-23 23:33

File

dann.lst

void){for(;;);} 108 .LM13: 109 /* prologue: frame size=0 */ 110 0020 C0E0 ldi r28,lo8(__stack - 0) 111 0022 D0E0 ldi r29,hi8(__stack - 0) 112 0024 DEBF out __SP_H__,r29 113 0026 CDBF out __SP_L__,r28 114 /* prologue end (size=4) */ 115 .L11: 116 0028 FFCF rjmp .L11 117 /* epilogue: frame size=0 */ 118

in „Welchen WINAVR nehmen ?“ · Mikrocontroller und Digitale Elektronik · 2006-10-11 21:59

File

1.c

* 100 */ 105, /* 101 */ 106, /* 102 */ 107, /* 103 */ 108, /* 104 */ 109, /* 105 */ 110, /* 106 */ 111, /* 107 */ 112, /* 108 */ 113, /* 109 */ 114, /* 110 */ 115, /* 111 */ 116, /* 112 */ 117, /* 113 */ 118, /* 114 */ 119, /* 115 */ 120, /* 116 */ 121, /* 117 */ 122, /* 118 */ 123, /* 119 */ 124, /*

in „Wie große Look-Up-Table erstellen?“ · Mikrocontroller und Digitale Elektronik · 2011-09-20 19:35

File

FW_Update_USB.c

IPU, Out 1 GPIOD->CRL = 0x33bb1884; // aus App und Boot-Jumper Pin1 (PD1 CanTX) GPIOD->CRH = 0x1111b111; // aus App // HW_Out_WegFreigabe(void){GPIO_WriteBit(GPIOD, GPIO_Pin_10, uHW_Out.bits.o_REZ);} FW_Timer = 0x100; while(FW_Timer--); // Warten bis der Pin Hi ist u16 FW_Pin_Loop = 0, FW_Pin_High = 0

in „GCC kompiliert falsch?“ · Mikrocontroller und Digitale Elektronik · 2011-06-29 19:57

File

madd-b.s

length = 1] add r24,r23 ; 25 addqi3/1 [length = 1] add r24,r22 ; 28 addqi3/1 [length = 1] mov r21,r24 ; 111 *movqi/1 [length = 1] lsl r21 ; 30 *ashlqi3/3 [length = 1] add r21,r24 ; 32 addqi3/1 [length = 1] lsl r21 ; 33 *ashlqi3/3 [length = 1] add r21,r18 ; 35 addqi3/1 [length = 1] ldi r24,lo8(-51) ; 37 *movqi

in „direkter Zugriff auf Low/High Byte von 16bit-Werten“ · Mikrocontroller und Digitale Elektronik · 2011-09-14 19:13

File

LED_Kerze.c

F_PWM*PWM_STEPS)) // Systemtakte pro PWM-Takt //#define T_PWM 1 //TEST #if ((T_PWM*PWM_PRESCALER)<(111+5)) #error T_PWM zu klein, F_CPU muss vergrösst werden oder F_PWM oder PWM_STEPS verkleinert werden #endif #if ((T_PWM*PWM_STEPS)>65535) #error Periodendauer der PWM zu gross! F_PWM oder PWM_PRESCALER

in „Aussetzer bei einfacher Soft-PWM Anwendung“ · Mikrocontroller und Digitale Elektronik · 2012-04-19 21:36

File

control_pomme.vhd

(shift_reg(137) xor shift_reg(116)); when 140 => shift_reg(1) <= not (shift_reg(140) xor shift_reg(111)); when 142 => shift_reg(1) <= not (shift_reg(142) xor shift_reg(121)); when 145 => shift_reg(1) <= not (shift_reg(145) xor shift_reg( 93)); when 148 => shift_reg(1) <= not (shift_reg(148) xor shift_reg

in „SNAKE GAME VHDL“ · FPGA, VHDL & Verilog · 2018-01-03 11:52

File

code1.vhdl.txt

byte_sub Port map (cypher1(119 downto 112),gclock,rst,e1,e2,data2); A3 : byte_sub Port map (cypher1(111 downto 104),gclock,rst,e1,e2,data3); A4 : byte_sub Port map (cypher1(103 downto 96),gclock,rst,e1,e2,data4); A5 : byte_sub Port map (cypher1(95 downto 88),gclock,rst,e1,e2,data5); A6 : byte_sub Port

in „VHDL coding Question“ · FPGA, VHDL & Verilog · 2014-11-27 06:47

File

ascii-set-4.h

0x08, 0xfe, 0x09, 0x09, 0x02, 0x00, 0x18, 0xa4, 0xa4, 0xa4, 0x7c, 0x00, // f und g // Zeichen 104 bis 111 0x7f, 0x08, 0x04, 0x04, 0x78, 0x00, 0x00, 0x44, 0x7d, 0x40, 0x00, 0x00, // h und i 0x40, 0x80, 0x84, 0x7d, 0x00, 0x00, 0x7f, 0x10, 0x28, 0x44, 0x00, 0x00, // j und k 0x00, 0x41, 0x7f, 0x40, 0x00, 0x00

in „daten in den flash,welche include datei“ · Mikrocontroller und Digitale Elektronik · 2006-10-12 03:56

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