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Forum: FPGA, VHDL & Verilog Issue with inout ports


Author: bob (Guest)
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Hi everyone,

I have some troubles with the codes in attachment. When I compile, these 
following errors are occuring:

ncelab: *E,CSGMSS: multiple sources for unresolved signal: INOUT_1B1_TB 
[4.3.1.2].
           Computing driving value: :CBTLV3253_tb(archi):inout_1B1_tb
In port map at: ../TBENCH/CBTLV3253_tb.vhdl, line: 52, position: 51
ncelab: *E,CSGMSS: multiple sources for unresolved signal: INOUT_1B2_TB 
[4.3.1.2].
           Computing driving value: :CBTLV3253_tb(archi):inout_1B2_tb
In port map at: ../TBENCH/CBTLV3253_tb.vhdl, line: 53, position: 30
ncelab: *E,CSGMSS: multiple sources for unresolved signal: INOUT_1B3_TB 
[4.3.1.2].
           Computing driving value: :CBTLV3253_tb(archi):inout_1B3_tb
In port map at: ../TBENCH/CBTLV3253_tb.vhdl, line: 54, position: 30
ncelab: *E,CSGMSS: multiple sources for unresolved signal: INOUT_1B4_TB 
[4.3.1.2].
           Computing driving value: :CBTLV3253_tb(archi):inout_1B4_tb


I tried to modify the ports "inout_1B1, inout_1B2, inout_1B3, inout_1B4" 
in inputs and "inout_1A" in output and that gave me good results.

So do you know why I have these errors ?

Thank you!

Author: Lothar Miller (lkmiller) (Moderator)
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bob wrote:
> multiple sources
> So do you know why I have these errors ?
A real value cannot be driven from two sources because there is no 
resolution table (like std_logic has one). So you get a conflict here:
        inout_1B1 => inout_1B1_tb
:
        in_1OEn_tb    <= '1';
  inout_1B1_tb  <= 1.0;
:
        if (in_1OEn = '1') then
     inout_1B1 <= 0.0;

But even when you "correct" that minor problem with the enable polarity: 
in eafch process the value of a signal remains "stored" until it is 
changed. So even after no more assigning a value to inout_1B1_tb it 
keeps the 1.0. And that will conflict further on with the value assigned 
to inout_1B1.

To keep it short: with real (and eg. integer) you cannot use 
bidrectional ports, because they don't have a resolution table to 
resolve access contentions.


BTW: next time to get syntax highlighting pls. attach *.vhd files, not 
*.txt files!

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