library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity CBTLV3253 is port( inout_1B1 : inout real; inout_1B2 : inout real; inout_1B3 : inout real; inout_1B4 : inout real; in_1OEn : in std_logic; inout_1A : inout real; S1, S0 : in std_logic ); end CBTLV3253; architecture archi of CBTLV3253 is begin process(in_1OEn, S1, S0) begin if (in_1OEn = '1') then inout_1A <= 0.0; inout_1B1 <= 0.0; inout_1B2 <= 0.0; inout_1B3 <= 0.0; inout_1B4 <= 0.0; elsif (in_1OEn = '0') then if (S1 = '0' and S0 = '0') then inout_1A <= inout_1B1; elsif (S1 = '0' and S0 = '1') then inout_1A <= inout_1B2; elsif (S1 = '1' and S0 = '0') then inout_1A <= inout_1B3; elsif (S1 = '1' and S0 = '1') then inout_1A <= inout_1B4; end if; end if; end process; end archi;