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Forum: FPGA, VHDL & Verilog 2 4-bit-adder modules to make an 8-bit adder


Author: CCC CCC (mcg)
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I have a problem with this question. I need these project and I will use 
just the main file. Is there anybody who will help me ?
Thanks ?

Question:
main file in which you use 2 4-bit-adder modules to make an 8-bit adder

Author: Lothar Miller (lkmiller) (Moderator)
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Show what you have done and point out the problem with it. Then maybe 
one will help you with your homework. At least we could see, which HDL 
you address...

Author: CCC CCC (mcg)
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I have these 2 4-bit's adder module. How can I combined and merged these 
in main file for obtain 8-bit adder ?

Author: Lothar Miller (lkmiller) (Moderator)
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CCC CCC wrote:
> I have these 2 4-bit's adder module.
Whats the difference between them?
As far as I can see both of those modules are similar 1 bit full adders. 
So you must chain up 8 of them to get the desired 8 bit adder.

Author: TB (Guest)
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Is this code even compiling without declaring S and Cout as "reg"? 
Anyhow at best, these are one bit full adders, as already mentioned by 
Lothar.

Author: CCC CCC (mcg)
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How can I obtain 8Bit full adder from 2 4-bit full adder ?
I found this code for 4-bit full adder and I tried to combined them but 
i didn't do this.
module fullAdder(
         input a,
         input b,
         input cin,
         output s,
         output cout );

        assign {cout,s} = a + b + cin;

endmodule

Could you help me how can I obtain this ?

Author: bko (Guest)
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how to connect instantiated modules by name:
http://www.asic-world.com/verilog/syntax2.html

e.g a two bit adder:
module adder_2bit(
         input [1:0] abus,
         input [1:0] bbus,
         input cin,
         output [1:0] sumbus,
         output cout );

  wire ctemp1;

   fullAdder u0 (
           .a(abus[0])      ,
           .b(bbus[0])      ,
           .cin(ci)      ,
           .sum(sumbus[0])    ,
           .cout(ctemp1)
           );
   fullAdder u1 (
           .a(abus[1])      ,
           .b(bbus[1])      ,
           .cin(ctemp1)      ,
           .sum(sumbus[1])    ,
           .cout(cout)
           );
endmodule

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