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Forum: FPGA, VHDL & Verilog use the output from counter


Author: basma hassan (Guest)
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hi all,,,,,,,,,,,,,
if i want to use the result from the counter and the result from 
accumulator
how can i make it in vhdl code.i want help plz.

Author: Mirco (Guest)
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Hi,

i guess u should specify your problem / task. Where do you want to use 
the output / for what purpuse ?

Author: ahmedhassan (Guest)
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Mirco wrote:
> Hi,
>
> i guess u should specify your problem / task. Where do you want to use
> the output / for what purpose ?

if i have input data i want to know their numbers , so i used a counter 
it gave me result such as (1,2,3,4...200)
and i want to sum these input data ,so i used accumulator gave me the 
result as (7,10,20,50....100) OK
i know there is only one value for counter(200) and the accumulator(100)
and then i want to divide 100/200,but when i make it in vhdl code .
it divide every value in accumulator to the corresponding value in 
counter such as (7/1,10/2,......100/200), so i need to specify the 
result from counter and accumulator how can i make it?

Author: Bitflüsterer (Guest)
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You should first clear your mind about what your name is. How could we 
hope to sucessfully help somebody who didn't even know whether his name 
is Basma or Ahmed? :-)

Author: Mirco (Guest)
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ahmedhassan wrote:
> so i need to specify the
> result from counter and accumulator how can i make it?

If Then Endif?

Author: ahmedhassan (Guest)
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Bitflüsterer wrote:
> You should first clear your mind about what your name is. How
> could we
> hope to sucessfully help somebody who didn't even know whether his name
> is Basma or Ahmed? :-)

what ever am i, i asked a question if you can gave me a hand do it or 
stop talking like this

Author: Bitflüsterer (Guest)
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> ... do it or stop talking like this

Don't command me to do or to omit something. I will not obey. I do what 
I do.

---
OK. Let's see what you are able to understand and realize. Just a try, 
because I'm curious.

You shall have a clock in your design which controls at which points in 
time the input is sampled from input into a register or added to the 
contents of an accumulator.

That's the first point. You have a clock. At certain moments (usually an 
edge) something happens. Is that clear for you?

If yes? Let's see your code. How did you express that?

Then you need some criteria to decide when, in the flow of time, you 
wan't the FPGA to perform the division. It's, what you allready wrote: a 
certain value of the counter.

That's the second point. You have a register (the counter) of which a 
certain value shall trigger an operation (the division). Is that clear?

If yes? Let's see your code. How did you express that?

Then you need to consider that there is a delay between the clock event 
which triggers the addition and the moment at which the result of that 
addition is available. This is true for the counter (which counts +1 +1 
+1 aso) as well as for the accumulator.

That's the third point. Relations are not realized instantaneously. They 
need time to take place.

As a consequence of the previous statements you need to consider, that 
you may possibly ever perform the division but disregard the result 
until a certain point in time which is expressed partly by the counters 
value. Otherwise you may choose to perform the division only at one 
point in time with the same criteria.

Is that clear?

As another consequence of the previous statements and the fact that 
virtually all actions in an FPGA-Design are triggered by a clock event, 
you need to have a second clock signal which is, so to say, "embedded" 
in or appended to the first clock, which triggers the addition of input 
values and increase of the counter. You can't perform the addition at 
the same moment in time in which you perform division, expecting to get 
a result incorporating the new sum and the new counter, because the 
addition just to about to be performed as well as the increment of the 
counter. This is not done yet.

Is that clear? If yes, let's see your code, which reflects that.

But however, you may trigger the division at the same moment when you 
trigger addition and counter increment, which will provide you with the 
result regarding the previous sum and the previous counter.
If you continue clocking that division, you will get the desired 
division at a point delta t + 1 in time.
It depends a bit, if this is appropriate to your needs, but you did not 
specify anything about it.

Is that clear? If yes, let's see your code.

Please post each code individually. Not the only the final result. It 
will be easier to discuss each point as it does not interfere with later 
points.

Author: Bitflüsterer (Guest)
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OK. And as a check for your comprehension:

I wrote: "You have a register (the counter) of which a certain value 
shall trigger an operation (the division)."

What is essentially wrong with this statement regarding the part 
"trigger an operation"? What do you trigger (cause, enforce) instead?

Author: ahmedhassan (Guest)
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you know , you make it difficult to me instead of make it easy anyway 
thanks a lot.

Author: Bitflüsterer (Guest)
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> ... you make it difficult to me ...

Possibly. But the reason lies within you, I think. Not me. There is some 
basic knowledge which one shall have, before making even the simplest 
attempt, to write some VHDL-code. You may not have it, but this not my 
responsibility. At least not, if you don't clearly state what the very 
problem is.

Taking it literally what you said, it is a matter of knowing how to 
assign a signal to another. That is one of the ways "to use" a signal. 
This is done by writing
Signal1 <= Signal2;

Checking a signal for a certain value in order to make another 
expression or statement depending on it is written:
if (signal3 = "001") then
   Signal1 <= Signal2;
end if;

That is another way "to use" a signal.

Making something dependent on a clock edge ist written:
if (rising_edge(clk)) then
   Signal1 <= Signal2;
end if;

That's even so a way "to use" a signal.

These are very basic issues.
Not knowing that would only be reasonable if you either have no access 
to the internet (which is obviously wrong) or not being able to 
understand texts which do explain that.

In the latter case it is your responsability to provide us with 
elaborated details about what you don't understand. Not by just confront 
us with your problem in general and let us solve your problem.

We are willing to help, but not act for you. You have the problem not 
us. We will not provide just a solution at your request. But we will 
help you to solve the problem yourself.


And at last: If you find that difficult, that's no wonder. It is 
difficult. And it is much more difficult to talk about that matters in 
natural language. Don't blame me. Blame reality.

Author: Achim S. (Guest)
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Hello Basma or Ahmed,

still dealing with the same problem linked below, correct?
http://embdev.net/topic/324276#3532491

Your problem description still remains unclear, and that is the real 
root of your trouble: you can't describe your problem clearly because 
you don't understand your problem yourself clearly. Think through your 
problem step by step, the you find the solution yourself. Your actual 
approach "I don't really understand what to do, but I need it done 
immediately" just wastes your time.

So let me try to guess (based on your many partial-descriptions) what I 
believe your problem is:

You have two counters. Each of them counts the number of samples 
arriving in two data-streams.
The value of the counters vary over time. Whenever a new data sample 
arrives, the value of the corresponding counter changes.
"In the end" you are interested in the ratio=counter1/counter2. But if 
you just describe it like you did in your assumed VHDL-code,then your 
simulation will show a new value of ratio always one clk cylce after a 
new sample arrived.
That's because in your assumed code the division does not know, if the 
latest sample also was the last sample, or if there are still further 
samples coming in. Your division always give you the ratio of the number 
of samples "up to now".
Therefor you have to define some criteria to let the division know, if 
it should execute or not.

If you have a trigger-signal telling you, that the last sample has 
arrived, then you need something simple like

if trigger_last = '1' then
   ratio<=counter1/counter2;
else
   ratio does not change
end if;

If you have no criteria at all wether the last sample alredy has 
arrived, then how should your division know when to execute?

Besides that you should be aware, that a division may be simple in 
simulation, but will be harder to implement in real hardware.

Author: ahmedhassan (Guest)
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hello achim
really you help me so much where i am not talking english very well and 
they blamed me that i did not know any thing about my problem,but i know 
its my fault to explain the task anyway thanks for help me,i will do 
what you suggested and feedback.

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