Forum: FPGA, VHDL & Verilog RAM not working as needed in spartan 3

Author: vhdl newbie (Company: none) (pranoy)
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hi guys,

       i've used this code as a ram block in Spartan 3. But it was not 
i checked the RTL view of the file, but in that the RAM block have 2 
pins unassigned(ENA and RSTA).

is that the problem why this is not working?

also the RAM created is a dual port RAM. I need only a single port RAM.

please help.

thanks in advance.

Author: Lothar Miller (lkmiller) (Moderator)
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vhdl newbie wrote:
>         data_o <= "ZZZZZZZZ";
This is not possible inside a FPGA. There are no tristate lines in 
FPGAs anymore.

> i've used this code as a ram block in Spartan 3.
Where did you take it from? Did you check out the templates Xilinx 
delivers with the ISE? And did you check the XST User Guide? In there 
you can find how to describe a RAM so that the synthesizer can recognize 
it correctly...

Author: alex (Guest)
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do you test it?
no --> testbench.

i would generate a bram with the core genarator from xilinx and check 
the function.


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