library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; entity ram_example is port (Clk : in std_logic; address : in std_logic_vector(3 downto 0); we : in std_logic; ram_enable:in std_logic; data_i : in std_logic_vector(7 downto 0); data_o : out std_logic_vector(7 downto 0); enter:in std_logic ); end ram_example; architecture Behavioral of ram_example is --Declaration of type and signal of a 256 element RAM --with each element being 8 bit wide. type ram_t is array (0 to 15) of std_logic_vector(7 downto 0); signal ram : ram_t := (others => (others => 'Z')); begin --process for read and write operation. PROCESS(Clk) BEGIN if(rising_edge(Clk)) then if(ram_enable='1')then if(we='1') then if(enter='1') then ram(conv_integer(address)) <= data_i; end if; data_o <= "ZZZZZZZZ"; elsif (we='0') then data_o <= ram(conv_integer(address)); else data_o <= "ZZZZZZZZ"; end if; end if; --else --data_o <= "ZZZZZZZZ"; end if; END PROCESS; end Behavioral;