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Forum: FPGA, VHDL & Verilog PROBLEM WITH CONNECTING SIGNALS ALU TO 4BITADDERSUB


Author: Xilinx VHDL (mikro2013)
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Hi!
I have a problem to creat ALU function  with 4bit full adder/sub like 
A-B , A xor B ,itc, .

ALU is defined with A,B(inputs 4bit) then K selected input (2bit) and  R 
output 4bit
4bit full adder/sub is defined with M,N inputs 4bit,S,COUT output 4bit,
 SO in selected but hi is 1bit!!!
And I have problem to connect K with SO because K is 2bit and SO is 
1bit!!!

I dont know how to connect this signals?

I attached files

AND I KNOW HOW TO DO LATER FUCTIONS A XOR B A-B A . WITH CASE but i don 
t know to connect signals K and SO

Author: Hmm (Guest)
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The main possibility starts with a third entity which instantiates alu 
and accu but contains also "signals". (Please read your script about 
it).

Author: PittyJ (Guest)
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I don't unterstand the full-adders?

Why can't you use the simple + operation, which adds numbers in VHDL?

Author: Xilinx VHDL (mikro2013)
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I'm so sorry! I uploaded wrong four_alu.vhd file :).
Now is four_bit_alu file.

Can I use the port map for connceting signals(or if you want, inputs and 
outputs and select in) between alu and four bit adder/sub?
And,again, how to connect SO with K which is 2bit (K(0),K(1))?

Thanks

Author: Lothar Miller (lkmiller) (Moderator)
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> four_bit_alu.txt
> I uploaded wrong four_alu.vhd file :)
You did so.
MY vhdl files extension is *.vhd or *.vhdl, but never *.txt

> I have problem to connect K with SO because K is 2bit and SO is 1bit!!!
> I dont know how to connect this signals?
Indeed you don't!
What function has S0?
What function has K?
Why at all sholuld you ever need to connect them?
Draw a schematic of your structure first. And then write vhdl code that 
does the wiring as you have scetched in your schematic.

PittyJ wrote:
> Why can't you use the simple + operation, which adds numbers in VHDL?
I see a lot of such low level structural vhdl code form schools around 
the world. And everybody has to build a kind of adder out of single 
gates. But indeed its a stupid task, because the synthesis tool CAN 
handle such easy arithmetic operations itself. And i don't see, why 
ANYBODY must do such a 
"scetching-down-an-adder-on-paper-and-transfer-it-to-a-netlist" job.

Author: Lance (Guest)
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>I see a lot of such low level structural vhdl code form schools around
>the world. And everybody has to build a kind of adder out of single
>gates. But indeed its a stupid task, because the synthesis tool CAN
>handle such easy arithmetic operations itself. And i don't see, why
>ANYBODY must do such a
>"scetching-down-an-adder-on-paper-and-transfer-it-to-a-netlist" job.

So true!
You start in VHDL, read a book and see that adders are build from 
scratch, instead of a simple "+".
You think to yourself: There has to be a reason!
Later in the job you still find professionals instanciating Adder cores.

Author: Lothar Miller (lkmiller) (Moderator)
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> instanciating Adder cores
Ouch...

Author: mikro2013 (Guest)
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I have to creat ALU function like +,- ,itc with 4-bit adder sub .
So, I have to connect ALU with 4-bit adder sub ,then i have problem with 
signal K which is 2bit and hi is selected input of alu and i have S 
signal of 4bit adder sub which is also selected input but 1bit.
I must connect them because i don t have another way to connect this 2 
components. DO YOU UNDERSTAND NOW?

Author: Günter (Guest)
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> DO YOU UNDERSTAND NOW?

Your shift key seems to be stuck. You should get a new keyboard.

Author: Purinder A. (Guest)
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u muzt contact the i/os form the ALU to the signels in ur modul, so u 
creat S, K itc too corisponding signels in ur modul with fittings bits 
widths. than inrupts mite works to.

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