----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:02:18 02/13/2013 
-- Design Name: 
-- Module Name:    four_bit_alu - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity four_bit_alu is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           K : in  STD_LOGIC_VECTOR (1 downto 0);
           R : out  STD_LOGIC_VECTOR (3 downto 0));
end four_bit_alu;

architecture Behavioral of four_bit_alu is

begin
process(A,B,K)
begin
case K is 
when "00"=>
R<= A - B;
when "01"=>
R<=A xor B;
when "10"=>
R<=not A;
when "11"=>
R<=B-"0001";
when others =>
R<="0000";
end case;
end process;


end Behavioral;














--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   22:19:30 02/13/2013
-- Design Name:   
-- Module Name:   C:/Users/Wing Chun/alu/aluosam/dgsdgsf/four_alu/alu_tb.vhd
-- Project Name:  four_alu
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: four_bit_alu
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY alu_tb IS
END alu_tb;
 
ARCHITECTURE behavior OF alu_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT four_bit_alu
    PORT(
         A : IN  std_logic_vector(3 downto 0);
         B : IN  std_logic_vector(3 downto 0);
         K : IN  std_logic_vector(1 downto 0);
         R : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic_vector(3 downto 0) := (others => '0');
   signal B : std_logic_vector(3 downto 0) := (others => '0');
   signal K : std_logic_vector(1 downto 0) := (others => '0');

 	--Outputs
   signal R : std_logic_vector(3 downto 0);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: four_bit_alu PORT MAP (
          A => A,
          B => B,
          K => K,
          R => R
        );
 
  
   alu_tb: process
   begin		
      A<= "0000", "0101" after 200 ns,"0010" after 400 ns,"1010" after 600 ns,"0001" after 800 ns;
      B<= "1100","1000" after 200 ns, "0011" after 400 ns, "0100" after 600 ns,"1110" after 800 ns;
		K<= "00", "01" after 200 ns, "10" after 400 ns, "11" after 600 ns;
		
		

     
      wait;
   end process;

END;