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Forum: FPGA, VHDL & Verilog VHDL testbench


Author: alice ng (farramimie)
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hello friends,

I'm having problem while doing my testbench coding.
there is no error when check the syntax but my testbench input for clock 
and data input show the '0' waveform..it means no pulse..i edit my clock 
time but it also not work.
maybe i must do looping for the 'datain' process but i don't know.

i hope u guys will help me to solve this problem.
i'm really appreciate it.thanx..

Author: Lothar Miller (lkmiller) (Moderator)
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What toolchain do you use?
For how long did you let the simulation run?
Can you post a screenshot of the simulation waveform?

Author: alice ng (farramimie)
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i use GNU toolchain.
i'm also re-attach the coding that i try to do looping but the result 
still the same.
for your information i want the simulation run until 20ms it means 260 
cycle.
thanx for your helping.

Author: Lothar Miller (lkmiller) (Moderator)
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You are not simulating the testbench. Your top module is obviuosly a 
module called "par_encoder". At the blue bar in your screenshot there 
should be the "par_encoder_TB"...

> Attached files:
>    NEW_PARENCOD_TB.txt (2 KB, 0 downloads)
Pls attach *.vhd files, not *.txt files.
Then you will see some little magic called "syntax highlighting".

Author: alice ng (farramimie)
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so it means i run with wrong procedure and wrong file?
thanx sir for keep helping me.

Author: Duke Scarring (Guest)
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Ok. Let's try it with Modelsim:
~/par_testbench$ vlib work
bl5599@fwfi34:~/test/par_testbench$ vcom par_encoder.vhd
Model Technology ModelSim PE vcom 10.1 Compiler 2011.12 Dec  6 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity par_encoder
-- Compiling architecture Behavioral of par_encoder
~/par_testbench$ vcom par_encoder_TB.vhd
Model Technology ModelSim PE vcom 10.1 Compiler 2011.12 Dec  6 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity par_encoder_TB
-- Compiling architecture behavioral of par_encoder_TB
###### par_encoder_TB.vhd(42):             CLK1 : STD_LOGIC;
** Error: par_encoder_TB.vhd(42): near "CLK1": expecting BEGIN
Your testbench code didn't compile...
One edit later...
~/par_testbench$ vcom par_encoder_TB.vhd
Model Technology ModelSim PE vcom 10.1 Compiler 2011.12 Dec  6 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity par_encoder_TB
-- Compiling architecture behavioral of par_encoder_TB
###### par_encoder_TB.vhd(56):  variable I=NATURAL;
** Error: par_encoder_TB.vhd(56): near "=": expecting ':'
###### par_encoder_TB.vhd(115): END behavioral;
** Error: par_encoder_TB.vhd(115): VHDL Compiler exiting
One more edit...
~/par_testbench$ vcom par_encoder_TB.vhd
Model Technology ModelSim PE vcom 10.1 Compiler 2011.12 Dec  6 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity par_encoder_TB
-- Compiling architecture behavioral of par_encoder_TB
Looks good. Next step: fire up the simulator.
~/par_testbench$ vsim -gui par_encoder_TB

VSIM 1> add wave *
VSIM 2> run 1 ms
See results above.

Duke

Author: alice ng (farramimie)
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thanx both of you...
now i'm try using the modelsim software..
if have any problem i will share at this site..
thanx a lot..

Author: Duke Scarring (Guest)
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ISIM should also work without problem, but I'am more familiar with 
modelsim...

Duke

Author: Lothar Miller (lkmiller) (Moderator)
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Waht are those two clocks in your design?

Are they coming from independent sources (e.g. 10MHz and 25MHz)?
Then you will encounter major problems, because there are various VERY 
BIG design flaws in your code:
PARITY_EN: process (CLK1,CLK2)
  if (CLK1'event and CLK1='1')then 
     ...
  end if;

  if (CLK2'event and CLK2='1')then
     ...
  end if;
end process;
A two-clock-process, whow!
Where did you get this coding style from?
With some luck you will get it synthesized for real hardware (maybe).
But if so, you will likely encounter significant problem due to passing 
values across clock domain barriers without any synchronisation.

Author: imed (Guest)
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In your first wave, you let your simulation run for 1 us but your clock 
will have it's first rising edge after 37 us...
So let your simulation run longer (1 ms as did Duke under modelsim).

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