LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use std.TEXTIO.all;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY par_encoder_TB IS
END par_encoder_TB;

 
ARCHITECTURE behavioral OF par_encoder_TB IS 

		   CLK1 : STD_LOGIC;
         CLK2 : STD_LOGIC;
         DATAIN : STD_LOGIC;
         DATAOUT : STD_LOGIC;
         MONITOR1: NATURAL range 0 to 592;
         MONITOR2: NATURAL range 0 to 592;


    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT par_encoder
    PORT(
         CLK1 : in  STD_LOGIC;
         CLK2 : in STD_LOGIC ;
         DATAIN : in  STD_LOGIC;
         DATAOUT : out  STD_LOGIC;
         MONITOR1: out NATURAL range 0 to 592;
         MONITOR2: out NATURAL range 0 to 592);
			
    END COMPONENT;
	 
	variable I=NATURAL;

   --Inputs
   signal CLK1 : STD_LOGIC := '0';
   signal CLK2 : STD_LOGIC := '0';
   signal DATAIN : STD_LOGIC := '0';

 	--Outputs
   signal DATAOUT : STD_LOGIC;
   signal MONITOR1:  NATURAL range 0 to 592;
   signal MONITOR2:  NATURAL range 0 to 592;

   
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: par_encoder PORT MAP (
          CLK1 => CLK1,
          CLK2 => CLK2,
          DATAIN => DATAIN,
          DATAOUT => DATAOUT,
          MONITOR1 => MONITOR1,
          MONITOR2 => MONITOR2
        );

   -- Clock process definitions
   CLK1_process :process
   begin
		CLK1 <= '0';
		wait for 38461 ns;
		CLK1 <= '1';
		wait for 38461 ns;
   end process;
 
   CLK2_process :process
   begin
		CLK2 <= '0';
		wait for 37453 ns;
		CLK2 <= '1';
		wait for 37453 ns;
   end process;
 
   process
    begin
		
	for I in 0 to 130 loop
		wait for 76923 ns;
		
	end loop;
		
	DATAIN <= '0';				-- initialization
	wait for 76923 ns;
		
	DATAIN <= '1';				-- reset the circuit
	wait for 76923 ns;
		
      wait;
   end process;

END behavioral;