LIBRARY ieee; USE ieee.std_logic_1164.ALL; use std.TEXTIO.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY par_encoder_TB IS END par_encoder_TB; ARCHITECTURE Behavioral OF par_encoder_TB IS CLK1 : STD_LOGIC; CLK2 : STD_LOGIC; DATAIN : STD_LOGIC; DATAOUT : STD_LOGIC; MONITOR1: NATURAL range 0 to 592; MONITOR2: NATURAL range 0 to 592; -- Component Declaration for the Unit Under Test (UUT) COMPONENT par_encoder PORT( CLK1 : in STD_LOGIC; CLK2 : in STD_LOGIC ; DATAIN : in STD_LOGIC; DATAOUT : out STD_LOGIC; MONITOR1: out NATURAL range 0 to 592; MONITOR2: out NATURAL range 0 to 592); END COMPONENT; --Inputs signal CLK1 : STD_LOGIC := '0'; signal CLK2 : STD_LOGIC := '0'; signal DATAIN : STD_LOGIC := '0'; --Outputs signal DATAOUT : STD_LOGIC; signal MONITOR1: NATURAL range 0 to 592; signal MONITOR2: NATURAL range 0 to 592; BEGIN -- Instantiate the Unit Under Test (UUT) uut: par_encoder PORT MAP ( CLK1 => CLK1, CLK2 => CLK2, DATAIN => DATAIN, DATAOUT => DATAOUT, MONITOR1 => MONITOR1, MONITOR2 => MONITOR2 ); -- Clock process definitions CLK1_process :process begin CLK1 <= '0'; wait for 38461ns; -- 1 cycle=76923ns,76923ns/2=38461ns CLK1 <= '1'; wait for 38461ns; end process; CLK2_process :process begin CLK2 <= '0'; wait for 37453ns; --1 cycle=74906ns,74906ns/2=37453ns CLK2 <= '1'; wait for 37453ns; end process; process begin DATAIN <= '0'; -- total time need to produce is 20ms,so 38461ns*261cycle=10038300ns wait for 10038300 ns; DATAIN <= '1'; wait for 10038300 ns; --total time need to produce is 20ms,so 38461ns*261cycle=10038300ns. total=20.0766ms wait; end process; END Behavioral;