Edge Detector in Verilog

Using external signals as clock is not a good design practice. Only use the real clock signal for posedge or negedge. For normal (slow) signals (e.g. pixel_ready, adc_done or spi_csn) it's often necessary to use a synchronizer and an edge detector as you described.

Yes i understand little bit...Can we put clock signal in sensitivity list for sync and the signal for whoom i am detecting his posedge to be putted in if condition just like this

Always @(posedge clk) Begin If ( s==1 ) ..........

When posedge of s will be detected then we can do anytask...Is this right?

Asad Ur R. wrote:

Always @(posedge clk) Begin If ( s==1 ) ..........

I think this will only detect the high-level of s.

When posedge of s will be detected then we can do anytask...Is this right?

To detect an edge on signal 's', I would use something like this:

1

always @ (posedge clk)

2

begin

3

  if (( s == 1) and ( s_dly == 0))

4

  {

5

    // do something on rising s-edge

6

  }

7

  s_dly <= s;

8

end

Asad Ur R. wrote:

Simply put that signal in sensitivity of Always block and when posedge will come always block will run

You have a very software oriented view of HDL. In reality you won't get a "block" of something in hardware. And of course you won't get something that "runs" somehow. Instead in your FGPA you only have logic blocks (LUT) and D-flipflops to generate your own functions.

And when you look in the synthesizers user manual you will find that this code

1

always @ (posedge clk)

2

begin

3

...

4

end

is the "Verilog-Way" to describe a D-flipflop.

And no, it is not a good idea to write

1

always @ (posedge d)

2

begin

3

...

4

end

because then you will get the d flipflop also, but you will get the d on the clock input. So as desired the flipflop will be set with a rising edge of the d signal. But you will not find a reliable way to reset it properly.