Instantiate module in verilog

Thiều Quang A. (tuananh) OP 2024-02-26 04:57 #7611280

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Hi guys i have 2 module. Fisrt module is generating clock signal

module ClockGenerator( output reg clk );

// Define clock period parameters parameter CLK_PERIOD = 10; // Define the clock period in simulation time units

// Initialize clock initial begin clk = 1'b0; // Start with the clock low end

// Toggle the clock signal at every half of the period always #((CLK_PERIOD/2)) clk = ~clk;

endmodule

Secound module is counter to 16 then reset to 0 when it reach 16

module CounterAndReset( output reg [3:0] count, input wire clk, input wire reset );

// Define the maximum count value parameter MAX_COUNT = 4'b1111;

// Initialize count always @(posedge clk or posedge reset) begin if (reset) begin count <= 4'b0000; // Reset count to 0 end else begin if (count == MAX_COUNT) begin count <= 4'b0000; // Reset count to 0 when it reaches MAX_COUNT end else begin count <= count + 1; // Increment count end end end

endmodule

I want to ask is how to combine these to module together. Thanks all

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Rick D. (rickdangerus) 2024-02-26 10:58 #7611400

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Thiều Quang A. wrote:

I want to ask is how to combine these to module together.

I would use a top level module (top.v) and there you can instantiate both sub modules.

Untested example:

module top;

  reg main_clk;

  reg main_reset = 0;

  wire [3:0] main_count;

  ClockGenerator inst_1 (

    .clk(main_clk)

  CounterAndReset inst_2 (

    .clk(main_clk),

    .reset(main_reset),

    .count(main_count)

endmodule

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