help with uart

PEter wrote:

I am trying to send some data via UART. I have a shift register which stores a value for 24 clk cycles. Meanwhile I want this value to be sent via UART because after that the register will have another value saved into it. Is this even possible?

The Shiftregister 15 bits wide. Sending via uart requires two data bytes with 1 start and 1 stop bit each (8N1). So you will need to transmit 20 bits, and you have 24 clock cycles time. So if the UART transmits with a bit rate ~equal to the clock rate, yes then its possible. If the UART is slower, no.

PEter wrote:

Hello,

I am trying to send some data via UART. I have a shift register which

maybe you should look into uart.v in the zip file you attached to your post?

There seems to be WORKING UART implementation, so you only need to use it, and you are done.

First I would like to thank you both for answering.

1. Can I set the speed of UART or is this a fixed max value that I have to read in the datahseet of artix7 ? Or did you just mean the baud rate by this ?
2. I knew it will need 2 transfers of 8 bits for data and all the stop and start bits together shouldn't exceed the 24 clock cycles (if the UART speed is fast enoguh). So I understand that.
3. I do have a working uart but I don't know how to implement it into my project. At UNI we did that UART example but I don't know how to use it in my project. I would be grateful if you could have helped me out.

Thank you again for your replys

PEter wrote:

project. At UNI we did that UART example but I don't know how to use it in my project. I would be grateful if you could have helped me out.

you should have started so:

I have homework at the UNI where I need to use UART and I do not know how.

Please help me with my homework.

I am sorry but this is not a homework. I am trying to build a detector which will detect to which way the current is flowing. The only part from the UNI is the UART part.

PEter wrote:

I am sorry but this is not a homework. I am trying to build a detector which will detect to which way the current is flowing. The only part from the UNI is the UART part.

Well then USE the UART.v code, the uart is there just use it. If you do not know how to use a verilog module then use google.

As said I do not know how to implement it into my project therefore I am trying to find help here.

PEter wrote:

As said I do not know how to implement it into my project therefore I am trying to find help here.

And I did tell you to use google. OK I do it for you:

google: how to instatiate verilog modules I did this for you, and did take FIRST LINK

https://www.chipverify.com/verilog/verilog-module-instantiations

it explains how to use verilog modules. Just instatiate the uart_tx module and use it then as needed in your top-level design.

I tried many things. Now even that from the forum you have sent me. I can't figure it out.

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// Instantiate tx_uart module

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tx_uart #(.DATA_WIDTH(8), .FREQ(10000000), .BAUD(115200)) uart_tx_inst (

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    .i_clk(f_clk),

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    .i_rst(rst),

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    .i_data(Q_4),  // Data I want to send to UART

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    .i_valid(SR_en),

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    .o_tx(),  // Connect to  output (an external pin)

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    .o_busy(tx_busy)  // Connect to tx_busy 

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);

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wire tx_output_signal;

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assign tx_output_signal = uart_tx_inst.o_tx;

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endmodule

This is the code I added, since I only need to use TX. The problem is that I dont really understand what is going on here. Im trying to do a simulation but tx_output_signal is low at all times. Also tx_busy is set to busy all the time.

PEter wrote:

I tried many things. Now even that from the forum you have sent me. I can't figure it out.

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// Instantiate tx_uart module

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> tx_uart #(.DATA_WIDTH(8), .FREQ(10000000), .BAUD(115200)) uart_tx_inst (

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>     .i_clk(f_clk),

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>     .i_rst(rst),

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>     .i_data(Q_4),  // Data I want to send to UART

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>     .i_valid(SR_en),

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>     .o_tx(),  // Connect to  output (an external pin)

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here you should connect tx_output_signal and not use assign!!!!

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>     .o_busy(tx_busy)  // Connect to tx_busy

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> );

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> 

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> wire tx_output_signal;

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> assign tx_output_signal = uart_tx_inst.o_tx;

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> endmodule

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> 

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>

This is the code I added, since I only need to use TX. The problem is that I dont really understand what is going on here. Im trying to do a simulation but tx_output_signal is low at all times. Also tx_busy is set to busy all the time.

this is some weird way todo things. You should have see above, used the output signal in instantion.

how long is your VALID pulse? How long did you simulate? The UART will send 0 for START as long as one bit time at the beginning. But BEFORE valid going low output should be high for sure, and busy should be low after reset before valid

PEter wrote:

I tried many things. Now even that from the forum you have sent me. I can't figure it out. [code]// Instantiate tx_uart module tx_uart #(.DATA_WIDTH(8), .FREQ(10000000), .BAUD(115200)) uart_tx_inst ( .i_clk(f_clk), .i_rst(rst), .i_data(Q_4), // Data I want to send to UART .i_valid(SR_en), .o_tx(), // Connect to output (an external pin) .o_busy(tx_busy) // Connect to tx_busy );

it seems your uart_tx has major issue in the code, namely the START bit can be random length depending when you assert valid. But that is not yet your problem, you have some more issues to solve out. also it seems busy is never cleared.. but it should be low after reset until valid comes, then when it asserts it is asserted forever.

maybe get some better UART IP core, that works

here you should connect tx_output_signal and not use assign!!!! I dont know what you mean. I know that o.tx() is the serial data that will be transmitted. I just made tx_output_signal to try to simulate it but it didnt work.

I am running simulation for 1000ns. Data_valid should be positive when SR_en = 1 right ? .i_valid(SR_en)

In that case, SR_en is on for 40ns so the i_valid should be the same

I just want the variables from my module that I crated to be used in the module UART

I have SR (its counting clk cycles from ADC) which I need to be sent via UART. This data can be sent while SR_en = 1 and meanwhile i need tx_busy to be 1. I dont know how to do that.