What is the error in the code below and why does vivado output u

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity DDR is

  port (

      ALARM_TIME     : in std_logic_vector (3 downto 0);

      CURRENT_TIME   : in std_logic_vector (3 downto 0);

      SHOW_A      : in std_logic;

      -----

      DISPLAY      : out std_logic_vector (6 downto 0);

      SOUND_ALARM    : out std_logic

    );

end DDR;

architecture RTL of DDR is

  signal DISP_CURRENT  : std_logic_vector (6 downto 0);

  signal DISP_ALARM  : std_logic_vector (6 downto 0);

  begin

    DISP_CURRENT      <=   "0111111" when CURRENT_TIME="0000" else --0

              "0000110" when CURRENT_TIME="0001" else --1

              "1011011" when CURRENT_TIME="0010" else --2

              "1001111" when CURRENT_TIME="0011" else --3

              "1100110" when CURRENT_TIME="0100" else --4

              "1101101" when CURRENT_TIME="0101" else --5

              "1111101" when CURRENT_TIME="0110" else --6

              "0000111" when CURRENT_TIME="0111" else --7

              "1111111" when CURRENT_TIME="1000" else --8

              "1101111" when CURRENT_TIME="1001" else --9

              "1100011"   ;      

    DISP_ALARM       <=   "0111111" when ALARM_TIME="0000" else --0

              "0000110" when ALARM_TIME="0001" else --1

              "1011011" when ALARM_TIME="0010" else --2

              "1001111" when ALARM_TIME="0011" else --3

              "1100110" when ALARM_TIME="0100" else --4

              "1101101" when ALARM_TIME="0101" else --5

              "1111101" when ALARM_TIME="0110" else --6

              "0000111" when ALARM_TIME="0111" else --7

              "1111111" when ALARM_TIME="1000" else --8

              "1101111" when ALARM_TIME="1001" else --9

              "1100011"   ;            

  process (DISP_ALARM, SHOW_A, DISP_CURRENT) is

    begin

      if SHOW_A = '1' then

        DISPLAY <= DISP_ALARM;

      else 

        DISPLAY <= DISP_CURRENT;

      end if;

  end process;

  --DISPLAY     <= DISP_ALARM when SHOW_A = '1' else DISP_CURRENT; 

  SOUND_ALARM   <= '1' when DISP_ALARM = DISP_CURRENT else '0';

end RTL;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--library work;

--use work.P_DISP1.all;

entity t_DDR is

end t_DDR;

architecture RTL of t_DDR is

  component DDR is

    port (

        ALARM_TIME     : in std_logic_vector (3 downto 0);

        CURRENT_TIME   : in std_logic_vector (3 downto 0);

        SHOW_A      : in std_logic;

        -----

        DISPLAY      : out std_logic_vector (6 downto 0);

        SOUND_ALARM    : out std_logic

      );

  end component;

    signal ALARM_TIME     : std_logic_vector (3 downto 0);

    signal CURRENT_TIME   : std_logic_vector (3 downto 0);

    signal SHOW_A      : std_logic;

    signal DISPLAY      : std_logic_vector (6 downto 0);

    signal SOUND_ALARM    : std_logic;

    signal DISP_ALARM    : std_logic_vector (6 downto 0);

    signal DISP_CURRENT    : std_logic_vector (6 downto 0);

    begin

    uut : DDR port map

      (

        ALARM_TIME    => ALARM_TIME,

        CURRENT_TIME   => CURRENT_TIME,

        SHOW_A       => SHOW_A,

        DISPLAY       => DISPLAY,

        SOUND_ALARM   => SOUND_ALARM

      );

    process

      begin

        ALARM_TIME     <= "0110";

        CURRENT_TIME   <= "1001";

        SHOW_A       <= '1';

        wait for 20 ns;

--        DISP1(DISPLAY);

        ALARM_TIME     <= "0111";

        CURRENT_TIME   <= "1000";

        SHOW_A       <= '0';

        wait for 20 ns;

--        DISP1(DISPLAY);

        ALARM_TIME     <= "0011";

        CURRENT_TIME   <= "0000";

        SHOW_A       <= '1';

        wait for 20 ns;

--        DISP1(DISPLAY);

        ALARM_TIME     <= "0111";

        CURRENT_TIME   <= "0110";

        SHOW_A       <= '0';

        wait for 20 ns;

--        DISP1(DISPLAY);

        ALARM_TIME     <= "1001";

        CURRENT_TIME   <= "1001";

        SHOW_A       <= '1';

        wait for 20 ns;

--        DISP1(DISPLAY);    

      wait;

    end process;

  end RTL;