*CPLD or FPGA?* The main difference is that CPLDs are smaller than FPGAs, i.e. you can fit a lot more logic inside a FPGA than inside a CPLD. * CPLDs: address decoders, bus interfaces, simple memory controllers, (video) signal generators * FPGAs: complex CPUs, high speed I/O, signal processing, encryption *VHDL or Verilog?* The difference is mainly in syntax, you can get the same synthesis result with both languages. VHDL is more verbose than Verilog (which can be an advantage or disadvantage, depending on how you look at it). In Europe VHDL is much more widely used than Verilog, in the US Verilog seems to be slightly more popular. Basic rules for VHDL development See "http://embdev.net/articles/VHDL":http://embdev.net/articles/VHDL. Chip vendors * "Xilinx":http://www.xilinx.com * "Altera":http://www.altera.com * "Lattice":http://www.latticesemi.com * "Actel":http://www.actel.com Boards * also see the FPGA vendors' websites * "Digilent":http://www.digilentinc.com Tutorials * TODO IP Cores * "Opencores":http://opencores.org - CPUs, USB, Ethernet, encryption, ... If you want to suggest any additions to this post, please reply below.
Hi, I think this site would be helpfull. Here is some basic things and some more advanced. http://www.fpga4fun.com/
for verfication http://www.stefanvhdl.com/ a good simulator is the combination GHDL and GTKwave http://sourceforge.net/projects/ghdl-updates/ http://gtkwave.sourceforge.net/ I have written an introduction for this simulator http://www.dossmatik.de/ghdl/ghdl_unisim_eng.pdf
I found the book "Free Range VHDL" to be an excellent book about the language and also about best practices when writing VHDL code. Link: http://freerangefactory.org/shop.html#FreeRangeVHDL-Book Cheers, Warren
There are many FPGA projects and tutorials on fpga4student.com: http://www.fpga4student.com/ http://www.fpga4student.com/p/fpga-projects.html http://www.fpga4student.com/p/verilog-project.html http://www.fpga4student.com/p/vhdl-project.html http://www.fpga4student.com/2017/07/recommended-affordable-Xilinx-FPGA-boards-for-students.html
i programmed fbga with xp2 lattice chip to switch lvds from ipu and gpu. The screen resolution of 1440x900 and 1600x900 is good. but 1920x1200 results are bad. I think the data and clk channel n and p output from the chip is not good. You let me ask how I write code to ensure that clk and data out are good
I found these IP for Ethernet very useful: http://www.fpga-cores.com/ For those who likes C++ this is very good to fast and easily create CPU / RISC-V systems for FPGAs: http://www.fpga-cores.com/instant-soc/
Simple VHDL Editor with access to IP Core library: http://sba.accesus.com/software-tools/sba-creator SBA (Simple Bus Architecture): http://sba.accesus.com/ Some Open IP Cores for SBA: https://github.com/mriscoc/SBA-Library
A lot of FPGA-based processor cores. http://www.mycores.biz/ Project has some cores, C-to-assm and assm-to-binary compiller, debug system and kernel software. Multiprocessor cores, multithread cores.
I am creating a Youtube playlist for those who are interested to start/learn/try hardware-software codesign with Xilinx Zynq APSoC platform. There are already 40 Videos and hoping to add about 100 Videos from basic to advanced level. Basic background in Verilog and C programming are assumed. All source code are made available through git repo. https://lnkd.in/gnw7Au8
CPLD or FPGA? >The main difference is that CPLDs are smaller than FPGAs, >i.e. you can fit a lot more logic inside a FPGA than inside a CPLD. Main different CPLD from FPGA that : CPLD work immidiatly after power up FPGA after power up need time for load from external or internal flash memory. It's present some application wich need work immidiatly after power up and can be released only by CPLD. P.S. FPGA can lose it design and stop work after short time power down or power spike and need it reload. CPLD does not have this problem. Regards Alex.
:
Edited by User
@Alexander S. you really have no clue of these things! First, do your homework before stating things. Cheers :)
ktorkkelson wrote: > @Alexander S. you really have no clue of these things! Perhaps Wikipedia have clue of these things : The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be used for "boot loader" functions, before handing over control to other devices not having their own permanent program storage. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory. https://en.wikipedia.org/wiki/Complex_programmable_logic_device FPGA loads it from external memory (typically on every power-on) https://en.wikipedia.org/wiki/Field-programmable_gate_array
Vipin K. wrote: > I am creating a Youtube playlist for those who are interested to > start/learn/try hardware-software codesign with Xilinx Zynq APSoC > platform. There are already 40 Videos and hoping to add about 100 Videos > from basic to advanced level. Basic background in Verilog and C > programming are assumed. All source code are made available through git > repo. > > https://lnkd.in/gnw7Au8 Usually I put real ModelSim project which you can start and check simulation of design and see that design really work. You don't need to build ModelSim project and design TestBench file . ModelSim simulation tools you can download from Altera's site. Regards Alex.
:
Edited by User
If you are working with Wishbone Instant SoC now supports Wishbone in a very nice way. See https://www.fpga-cores.com/wishbone/
Watch this topic
Disable multi-page viewPlease log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
Log in with Google account
No account? Register here.