VHDL: BCD to Sevensegment

Tobias Hagenaars Guest #6872666
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Im a beginner at VHDL (vivado) and I have a task. Could someone explain 
to me why i have an error near signal which says: no viable alternative 
near input 'signal'. There is also an error near SevenSegm which says 
that its a duplicate declaration. Could someon explain to me what i have 
to do to fix this?
TY very much
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Lothar M. Moderator (Company: Titel) #6872712
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Tobias Hagenaars wrote:
> Could someone explain to me why i have an error near signal which says:
> no viable alternative near input 'signal'.
You always must look at the code just before the reported error also. 
Here the synthesizer does not expect the keyword "signal" in line 27 
after the comma in line 26.

BTW: instead of the unlit segments "1111111" in the lines 20 to 26 you 
could show the hex characters A, b, c, d, E, F on the 7 segment 
displays...
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