How to add two signals of type std_logic

Ashok M. wrote:
> A std_logic type cannot be converted to signed/unsigned type because
> that requires an array type.
Why digging in the mud and defining own "rules"?

The definition of a signed/unsigned ist very similar to that of a 
std_logic_vector, you can check that out the free available code of 
those packages:
https://www.csee.umbc.edu/portal/help/VHDL/packages/numeric_std.vhd

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Package numeric_std is

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--==================================================

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-- Numeric array type definitions

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--==================================================

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type UNSIGNED is array ( NATURAL range <> ) of STD_LOGIC;

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type SIGNED is array ( NATURAL range <> ) of STD_LOGIC;

And:
https://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_1164.vhd

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-------------------------------------------------------------------    

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-- unconstrained array of std_logic for use in declaring signal arrays

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-------------------------------------------------------------------    

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TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

> Any suggestions?
VHDL does not give room to laziness and implicity. Everything thats 
written must be written down explicitly.
Simply use the numeric_std package to cayst between std_logic_vector and 
signed/unsinged. And use the vesy same package to convert from integer 
to signed/unsinged and vice versa:
http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

The same picture also exists in english mutations.

> std_logic_vector (0 to 0);
You are taking all tricky steps at once: 1. a one element array 2. with 
very strange bit order...

Thanks very much for the solution. It worked. I come from Verilog 
background, and it is straight forward (loosely typed language) to add 
two single bits and assign result to a single bit (discarding the msb).

In line with your solution, I tried the following and that worked as 
well.

  variable G : std_logic_vector (1 downto 0);
  variable D, E : std_logic;
  variable uS1 : unsigned (1 downto 0);

  uS1 := unsigned'('0' & D) + unsigned'('0' & E);
  G := std_logic_vector(uS1);


Thanks.


FPGA NOTFALLSEELSORGE wrote:
> But ... it can be done, add two std_logic and get one std_logic_vector(1
> downto 0).
>
>

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library ieee;

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> use ieee.std_logic_1164.all;

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> use ieee.numeric_std.all;

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> 

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> entity tb_add_std_logic is

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> end tb_add_std_logic;

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> 

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> architecture tb of tb_add_std_logic is

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> 

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> constant dummy : unsigned(1 downto 0):="00";

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> signal D : std_logic:='0';

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> signal E : std_logic:='0';

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> signal F : std_logic_vector(1 downto 0):="00";

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> 

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> begin

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> 

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> D <= not D after 10 ns;

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> E <= not E after 13 ns;

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> 

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> F <= std_logic_vector(dummy + (""&D) + (""&E));

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> 

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> end;