Hello, I understand that you cannot add two std_logic_vector types because a std_logic_vector does not have a numeric value. You have to convert std_logic_vector to signed/unsigned; do the math operation and convert result back to std_logic_vector. But how do you add two signals of type std_logic? A std_logic type cannot be converted to signed/unsigned type because that requires an array type. I tried the following signal D, E, F : std_logic; signal G : std_logic_vector (0 to 0); begin Monitor: process is begin D <= '1'; E <= '0'; --F <= D + E; --Compile Error - D and E are not numeric values. --F <= unsigned(D); --Compile Error - D must be an array type. --F <= unsigned(G); --NO --G <= '1'; --NO Any suggestions? Thanks very much.
Ashok M. wrote: > A std_logic type cannot be converted to signed/unsigned type because > that requires an array type. Why digging in the mud and defining own "rules"? The definition of a signed/unsigned ist very similar to that of a std_logic_vector, you can check that out the free available code of those packages: https://www.csee.umbc.edu/portal/help/VHDL/packages/numeric_std.vhd
1 | Package numeric_std is |
2 | --==================================================
|
3 | -- Numeric array type definitions
|
4 | --==================================================
|
5 | type UNSIGNED is array ( NATURAL range <> ) of STD_LOGIC; |
6 | type SIGNED is array ( NATURAL range <> ) of STD_LOGIC; |
And: https://www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_1164.vhd
1 | -------------------------------------------------------------------
|
2 | -- unconstrained array of std_logic for use in declaring signal arrays
|
3 | -------------------------------------------------------------------
|
4 | TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; |
> Any suggestions? VHDL does not give room to laziness and implicity. Everything thats written must be written down explicitly. Simply use the numeric_std package to cayst between std_logic_vector and signed/unsinged. And use the vesy same package to convert from integer to signed/unsinged and vice versa: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std The same picture also exists in english mutations. > std_logic_vector (0 to 0); You are taking all tricky steps at once: 1. a one element array 2. with very strange bit order...
:
Edited by Moderator
Ashok M. wrote: > F <= D + E; --Compile Error - D and E are not numeric values. Sure! But what do you expect? D and E are one Bit each and F is also only one Bit. So how should addition work? What is '1' + '1'? If you say 2 this is "10" and will not fit in the single Bit of F. Ashok M. wrote: > G <= '1'; --NO G <= "1";
Attached files:
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add_std_logic.png
3.2 KB
But ... it can be done, add two std_logic and get one std_logic_vector(1 downto 0).
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.numeric_std.all; |
4 | |
5 | entity tb_add_std_logic is |
6 | end tb_add_std_logic; |
7 | |
8 | architecture tb of tb_add_std_logic is |
9 | |
10 | constant dummy : unsigned(1 downto 0):="00"; |
11 | signal D : std_logic:='0'; |
12 | signal E : std_logic:='0'; |
13 | signal F : std_logic_vector(1 downto 0):="00"; |
14 | |
15 | begin
|
16 | |
17 | D <= not D after 10 ns; |
18 | E <= not E after 13 ns; |
19 | |
20 | F <= std_logic_vector(dummy + (""&D) + (""&E)); |
21 | |
22 | end; |
Thanks very much for the solution. It worked. I come from Verilog
background, and it is straight forward (loosely typed language) to add
two single bits and assign result to a single bit (discarding the msb).
In line with your solution, I tried the following and that worked as
well.
variable G : std_logic_vector (1 downto 0);
variable D, E : std_logic;
variable uS1 : unsigned (1 downto 0);
uS1 := unsigned'('0' & D) + unsigned'('0' & E);
G := std_logic_vector(uS1);
Thanks.
FPGA NOTFALLSEELSORGE wrote:
> But ... it can be done, add two std_logic and get one std_logic_vector(1
> downto 0).
>
>1 | library ieee; |
2 | > use ieee.std_logic_1164.all; |
3 | > use ieee.numeric_std.all; |
4 | >
|
5 | > entity tb_add_std_logic is |
6 | > end tb_add_std_logic; |
7 | >
|
8 | > architecture tb of tb_add_std_logic is |
9 | >
|
10 | > constant dummy : unsigned(1 downto 0):="00"; |
11 | > signal D : std_logic:='0'; |
12 | > signal E : std_logic:='0'; |
13 | > signal F : std_logic_vector(1 downto 0):="00"; |
14 | >
|
15 | > begin |
16 | >
|
17 | > D <= not D after 10 ns; |
18 | > E <= not E after 13 ns; |
19 | >
|
20 | > F <= std_logic_vector(dummy + (""&D) + (""&E)); |
21 | >
|
22 | > end; |
You can write:
1 | F <= std_logic_vector(unsigned'('0' & D) + unsigned'('0' & E)); |
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